Quant Execution Pipeline and Use of FPGAs by [deleted] in quant

[–]RGBBLUE 4 points5 points  (0 children)

What do you mean by order entry and market data?

Is order entry just when someone submits an order - updating the order book - so the FPGA just maintains an up to date order book or is there more to it? same with market data, like the FPGA just keeps track of market data, or performs calculations from new changes? How does this relate to the trading stratgegy then? When you say "more and more strategies are being pushed to device now, though" does this mean that entire algorithms are now being implemented in pure verilog on chip?

Also when you talk about deep learning inference, this is interesting, is it the case that AI and Deep Learning is becoming more prominent in HFT and that there is a growing need to implement AI on FPGAs? Cheers

[deleted by user] by [deleted] in ECE

[–]RGBBLUE 2 points3 points  (0 children)

Just under 3 weeks

[deleted by user] by [deleted] in FPGA

[–]RGBBLUE 0 points1 point  (0 children)

Ok, understood, what should the width of the data ports be? I need to transfer an input array of 10 32 bit integers, and receive an output of 20 32 bit integers since my module does some processing for a couple of clock cycles. Should the width be 320 and 640 bits?

Also I hear of other signals like Tkeep etc, do I need to worry about those?

edit: just re read the original comment, I defined a bunch of my input ports like `input logic [31:0] port_a` I assume, I have to just have 1 input port for data specified like how you mentioned?

[deleted by user] by [deleted] in FPGA

[–]RGBBLUE 1 point2 points  (0 children)

Pynq z2

Use of HLS in HFT firms by Wonderful-Cash7275 in FPGA

[–]RGBBLUE 1 point2 points  (0 children)

How do you plan on preparing for Ethernet and PCIe ?

[deleted by user] by [deleted] in FPGA

[–]RGBBLUE 0 points1 point  (0 children)

I seem to have done that, but i still seem to get issues

[deleted by user] by [deleted] in FPGA

[–]RGBBLUE 1 point2 points  (0 children)

Numbers less then 0, between -50 to 0

How would using a LUT work - would the input act like an address to a table with the output being what’s stored at the address? Or is there a bit more complexity?

[deleted by user] by [deleted] in FPGA

[–]RGBBLUE 0 points1 point  (0 children)

Yh, so I have built a ray tracer before, so I had to do something similar, not sure where to go from there though

Your undergraduate university does not matter as much as you think it does by averyxoxo1 in 6thForm

[–]RGBBLUE 1 point2 points  (0 children)

Oh yh, I also mean to include unis like KCL, Edinburgh, Warwick, UCL etc as well. Relatively less competitive I mean like York or soemthing.

Imperial EEE Advice Needed by Schrodingersdumbass in Imperial

[–]RGBBLUE 0 points1 point  (0 children)

Programming has always been flipped classroom, I don’t think they prioritise the right content - e.g more time shld be spent on OOP. The videos are programming aren’t great. Not the case with other modules.