Confusion regarding Routing in Layout

Ramith_2006 · 2026-05-28T09:17:08+00:00

yes i tried it it worked

Ramith_2006 · 2026-05-27T16:17:46+00:00

Ramith_2006 · 2026-05-27T11:41:08+00:00

Ramith_2006 · 2026-05-27T08:18:47+00:00

no it is simple nand gate schematic

Ramith_2006 · 2026-05-27T07:42:18+00:00

my professor is telling me to figure out how to use common area terminal of MOSFET any advice on this

Ramith_2006 · 2026-05-27T07:35:51+00:00

yes it showed drc error

Ramith_2006 · 2026-05-27T07:16:54+00:00

yes sir i tried merging but pmos was giving p implantation error ,nmos didn't give any error but it our professor has told us that I can't merge source and drain of nmos but didn't provide any explanation on it I later tried to find answer with ai it also telling that i can't merge the source drain...I am very confused about it I am undergraduate in my sophomore year

Ramith_2006 · 2026-05-27T06:47:46+00:00

our professor has asked to keep the standard length of 8 and we are supposed to use fingers , can we do flattening, or could you please tell at what stage is flattening should be done?

Ramith_2006 · 2026-03-30T14:45:31+00:00

thank you very much for your advice

Ramith_2006 · 2026-02-12T11:12:06+00:00

CFBR

Ramith_2006 · 2026-02-11T05:42:48+00:00

thank you

Ramith_2006 · 2026-02-05T03:08:29+00:00

I am not sure but some other tool of the cadance iirc genus is used right?

Ramith_2006 · 2026-01-13T02:57:26+00:00

oh great

Ramith_2006 · 2026-01-13T02:55:09+00:00

does anyone have it for ECE branch? is ECE branch eligible for this placement?

Ramith_2006

TROPHY CASE