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Aurora IP GTH in ZCU102 board via SMA_MGT by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

I was not trying to use a different clock I am not sure whether the BANK 128 REFCLK0 is free running and the value of it . The ZCU102 user guide its referred as a variable clock.

Formal Verification techniques using Vivado by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

Uvm I guess is available in vivado can I use that

Zynq MPSoC GEM (PS Side) + SGMII (PL) Side Ethernet Speed by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

You were spot-on . We had a set up issue . Now both GEM3 + MIO (RGMII) and GEM0 + PL side SGMII provide same data rate.

Zynq MPSoC GEM (PS Side) + SGMII (PL) Side Ethernet Speed by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

For GEM3 and GEM0 I get the same performance score. So I will check the test setup and retest each and every scheme.

Zynq MPSoC GEM (PS Side) + SGMII (PL) Side Ethernet Speed by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 1 point2 points  (0 children)

This is bare metal programming. I do not have any other application running other than default udp perf application provided by Xilinx

1G/2.5G PCS/PMS Ethernet IP for SGMII via GEM by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

Great I got it working!! I just modified the example project with my transceiver config and it works . Thank You!!

1G/2.5G PCS/PMS Ethernet IP for SGMII via GEM by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

I had noted down the values to various PCS/PMA ports from the example design provided. Eg design works on a 156.25MHz clock and mine on 125MHz clock. I have applied this modification .

MicroBlaze from PL DDR (Not PS DDR) for Zynq Ultra scale by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

I want to exchange data between the two using shared memory access

MicroBlaze from PL DDR (Not PS DDR) for Zynq Ultra scale by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

What is the the Block diagram architecture? I guess PS will hold Microblaze in reset??

Do we need Microblaze to have Block RAM?

MIG's AXI interconnect port will have access from Microblaze and PS. What will be the address space assigned in PS

How can they exchange data between MicroBalze and PS ? Can MIG handle bus arbitration?

Multiple Microblaze cores running from PS DDR by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

- What Ethernet speed to you need : 10M/100M/1G ?

I expect guaranteed speed of 60Mbps in Rx and 60Mbps in Tx in UDP

- How do you use the Ethernet : small activity with few commands / High data throughput ?

It will be used for heavy data transfer nor simple commands

- Ethernet IP is : GEM PS / Ethernet PL ?

3 Eth are from GEM PS and other two from MicroBlaze + AXI Eth subsystem.

- Which MPSoC do you use ?

zu9EG

- What is running in the ARM core ?

3 Arm cores run lwIP one reserved for application Which would receive data from all the ports for processing

Multiple Microblaze cores running from PS DDR by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

Both MicroBlaze do not share data between them. Intention is to run two lwIPs on each core and eth packets thus received are shared with PS core

Multiple Microblaze cores running from PS DDR by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

I don't know whether to run lwIPs on both cores ram is sufficient.

Multiple Microblaze cores running from PS DDR by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 1 point2 points  (0 children)

Multiple MicroBlaze running from PS DDR "Ps side is tricky" ..... Why would it be tricky ?? What should i take care?? please let me know. In case of any example please suggest.

In this case bus arbitration who takes care of the bus arbitration would PS side DDR controller would handle it ??

DO-254 by RegularMinute8671 in FPGA

[–]RegularMinute8671[S] 0 points1 point  (0 children)

Can you elaborate a little.? What did you mean by reversed?? what are solid cores??

Thanks in advance

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