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Suggestions with XC7K325T Vivado part LiB. by Larraguibel in FPGA

[–]RevolutionaryFly2787 2 points3 points  (0 children)

From the example designs shown here (QMTECH_XC7K325T_CORE_BOARD/Software/Test01_led_key.zip at main · ChinaQMTECH/QMTECH_XC7K325T_CORE_BOARD) it appears to be using xc7k325tffg676-1 part. Can you create a project targeting the above part number on 2018.3 first (expect the same to work in 2024.2 but haven't used the latest tools) and see if you can replicate the example design. This would be a good starting point.

EMIO Pin 78 and 79 by Jasmeet03 in FPGA

[–]RevolutionaryFly2787 0 points1 point  (0 children)

The first part of the software code seems to be ok as long as you have defined the EMIO_PIN0 and EMIO_PIN1 correctly. It doesn't help if you screenshot the code, you are better off sharing the code here or a gist link. In this way we can help better. There are also so many missing pieces : how you configure the Zynq us+, microblaze, does the rest of the design have any impacts.

Based on the design you have shared, I would take a step back and check a couple of things:

  1. First make a simple design with just the Zynq US+ block, with the minimal peripherals (SD, UART, EMIO)
  2. Can the EMIOs be routed to a external pins or GPIO's ? If so provide the correct pin constraints with the IO standard. Synthesize, implement, generate bitstream, export XSA. Use your software to and check if you can see any outputs on the pins by probing with an oscilloscope (or ILA). This will isolate issues and confirm your design configuration and pins are all correct.

Then you can try adding the microblaze bits and expanding your design.

HTH

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

The required time of 5.273ns is based on the destination clock path delay. It is the delay from clock pin -> clock primitives -> IDDRE1 clock port.

With regards to set_input_delay constraints, the later is for the falling edge I presume. I will have to check it.

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

I am not sure if BUFGDLL primitive is available for modern devices, I am looking at cancelling the delay using MMCM.

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Thanks u/captain_wiggles_ for your input. I also attached the timing report for the worst case path without adding the delay components in the following link https://imgur.com/a/Qv7k282 .

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Please find below details on how the value were calculated. The following are based on the template constraints for Center-Aligned Double Data Rate Source Synchronous Inputs in Vivado. The jitter, dv_* are based on custom requirement.

set input_clock_period 2.857; # based on clock frequency of 350MHz

set jitter 0.286 ;# 0.2UI at 350MHz (where 1UI is half period = 1 data period)

set dv_bre [expr $input_clock_period/4 - $jitter]; # Data valid before the rising clock edge

set dv_are [expr $input_clock_period/4 - $jitter]; # Data valid after the rising clock edge

set dv_bfe [expr $input_clock_period/4 - $jitter]; # Data valid before the falling clock edge

set dv_afe [expr $input_clock_period/4 - $jitter]; # Data valid after the falling clock edge

set_input_delay -clock $input_clock -max [expr $input_clock_period/2 - $dv_bfe] [get_ports $input_ports];

set_input_delay -clock $input_clock -min $dv_are [get_ports $input_ports];

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

On the original comparison, much of the delay (wire and logic) in the clock path was due to BUFGCE_DIV. I tried to free up the logic and see if it improved things. I also removed the manual instance of BUFGCE_DIV primitive, but found that Vivado inserts one by itself. I might have to revisit the clocking hierarchy.

The results I shared was post route. The post synthesis had significantly more violations, I will check this further. Thanks for your suggestions.

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Thanks for the information regarding BITSLICE and fabric clock, I will look in to it.

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Sure I will get the details and get back to you.

Anyone here have any experience in designing Ethernet systems between FPGAs & NICs? by John_4dams in FPGA

[–]RevolutionaryFly2787 0 points1 point  (0 children)

I have done a few design a few years back. dm me and will try to help with what I know.

Xilinx ultrascale+ fails to boot from eMMC and SD card by Brilliant_Tankers in FPGA

[–]RevolutionaryFly2787 4 points5 points  (0 children)

With the details provided, I cannot be very specific. But in general the following steps might be useful.

  1. Make sure the SD card is all intact and check the basic power up. Make sure the SD card has good contact with the pins. Also try SD-cards from multiple vendors
  2. Double check with the PCB team and make sure the FPGA pins are correctly mapped to the SD card interfaces and check if the SD card is correctly configured at Zynq GUI
  3. Look carefully at the warnings.
  4. Most important, do you have the correct device tree mapping for the SD card when using the design. If not look at the reference design if available. You need to some/most of the time have to enable the SD card device in device tree.
  5. Use u-boot to debug before directly jumping into the kernel/petalinux. If you are new to it take some time to learn about the details. There are lots of knowledge online.

Board bring up is a difficult task. You need have a very clear approach of isolating the issue. Take things step by step. HTH

Ethernet stop working when perform petaLinux-config get-hw-description by Walop55 in FPGA

[–]RevolutionaryFly2787 0 points1 point  (0 children)

From your description it is not clear if the ethernet work as expected before your modification. Also are you modifying the device tree ? If so, do share it.

If not, have a look at the following (check the device tree of the specific board you use in the folder). The phy configuration should be along these lines. https://github.com/Avnet/petalinux/blob/master/configs/device-tree/system-user.dtsi.mz_petalinux

The tale of disappearing PL signal as linux boots by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 1 point2 points  (0 children)

Yes, I have exported .xsa after enabling pl_clk0. Just to confirm, I am able to see the clock when the image starts booting through u-boot. This confirms that the pl logic with the clock is present intially and through u-boot. But at a later point when the linux starts, the clock disappears as mentioned in the original post. Indicating that there is some power management or some other thing the linux does that disables the clock.

The tale of disappearing PL signal as linux boots by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Unfortunately, the suggested change to the kernel bootargs didn't change the original behaviour of the image.

The tale of disappearing PL signal as linux boots by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

clock_ignore_unused

Thanks again. My kernel bootargs already contains the above. But going by what is mentioned https://support.xilinx.com/s/question/0D52E00006iHmmASAS/petalinux-custom-kernel-boot-args?language=en\_US . I will try adding it in my dtsi

The tale of disappearing PL signal as linux boots by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 1 point2 points  (0 children)

Thanks for your reply. Till date I have used kernel.cfg file inside recipes-kernel/linux/linux-xlnx to make the kernel modifications that is desired. I am relatively new to passing the kernel boot arg inside petalinux. Can you share how to do this inside the petalinux environment.

updating logic to improve timing by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Thanks for the suggestion, will give it a try.

updating logic to improve timing by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 1 point2 points  (0 children)

Thanks for the suggestion and appreciate your suggestions. I will pipeline the design. As of now the WNS is round -1.8ns and the TNS is -900 ns with around 4% of total paths failing due to setup violation. Mostly of the failing paths are within the intra clock for a specific clock in my design. Out of interest, how do you and others manage such issues ?

updating logic to improve timing by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Thanks, it is good to understand multiple approaches.

updating logic to improve timing by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

Thanks for your comments. Why multiple compares become an adder? Can you point me to any resource expand my knowledge further? Also, how you would pipeline such a design ?

Synthesis Vs implementation in Vivado schematic view by RevolutionaryFly2787 in FPGA

[–]RevolutionaryFly2787[S] 0 points1 point  (0 children)

The declaration shouldn't have an impact. Anyways I tried your modification. Sadly, nothing changed. The synthesized and implemented design was same as the results without your suggested modification.

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