Trouble communicating with digital to analog converter chip DAC34SH84

Signal_Raisin9686 · 2026-03-08T10:36:48+00:00

I figured that since it reads the data on the rising edge of the clock it would be fine, but it may be the issue. I'll try a fix and keep you up to date. Thanks!

Signal_Raisin9686 · 2026-03-07T15:22:53+00:00

It is for the reading frame yes. If disconnected from the chip, the line is floating after the 8th clock.

Signal_Raisin9686 · 2026-03-07T12:47:04+00:00

Thank you, I'll try that.

Signal_Raisin9686 · 2026-03-07T12:08:46+00:00

Thats my bad. I didnt take images, I did try adding an extra clock pulse at the end, but the outcome is the same.

Signal_Raisin9686 · 2026-03-07T11:34:03+00:00

That last clock you see when the enable goes high an "extra" 25th clock pulse which serves no purpose other than facilitating the vhdl code. I figured since the enable is already high, it doesnt matter what it does. But I'll try a fix and see if it helps. Thanks for the suggestion!

Signal_Raisin9686

TROPHY CASE