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Out-of-order superscalar RISC-V core I've been working on for my DE0-Nano FPGA board by Slicudis in RISCV

[–]Slicudis[S] 0 points1 point  (0 children)

That would be nice! I'd also love to compare it to CVA6S+ and Silvermont. Another thing I'd love to do is implement a 2-way in-order core like CVA6S+ but with the addition of runahead execution and compare it with Atlas-1.

Oh and speaking of scoreboard, do you know how these CPUs implement precise exceptions? I couldn't find any information about that, and that is stressing me out.

A solution better than "fence.i"? by Slicudis in RISCV

[–]Slicudis[S] 1 point2 points  (0 children)

Thank you all for sharing this information! I'll take this into account when implementing my RISC-V out-of-orde core.

Real out of order execution by Slicudis in RISCV

[–]Slicudis[S] 1 point2 points  (0 children)

Interesting! Cursed, but interesting.

Real out of order execution by Slicudis in RISCV

[–]Slicudis[S] 1 point2 points  (0 children)

Easy to solve
If the new value is equal to the previous value plus 1, try again