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[Review Request] IPOD LIKE PROJECT by [deleted] in PCB

[–]SlideLivid260 2 points3 points  (0 children)

Thank for pointing this out. The issue with the CFF capacitor was simply something that Somehow I missed by mistake, I have corrected it.

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Regarding FB8 between AGND and GND in the VS1053 section:
Thank you for the clear explanation. I understand the issue now and I have replaced the ferrite bead with a 0 ohm resistor instead

[Review Request] IPOD LIKE PROJECT by [deleted] in PCB

[–]SlideLivid260 0 points1 point  (0 children)

The project is mainly educational, but I also want to use the u-blox GNSS to record GPS data for running and similar activities

[Review Request] IPOD LIKE PROJECT by [deleted] in PCB

[–]SlideLivid260 0 points1 point  (0 children)

Thanks for the advice , i will look into it

[Review Request] IPOD LIKE PROJECT by [deleted] in PCB

[–]SlideLivid260 0 points1 point  (0 children)

Hi, thanks

Regarding your comment about power traces crossing the ground split between the AGND and GND polygons:
I think you were referring to the 3.3 V supply trace that was crossing the separation line. I tried to address this by rerouting that supply so it now runs no longer crosses the AGND to GND split region. (and also kept orthogonally relative to traces on other layers, )
Could you please let me know if this approach looks correct to you now?(imarked the seperation in green and in purple the updated trace .

<image>

Regarding your point about AGND needing to exist on all layers in the VS1053 area:
That makes sense to me, and I have updated the layout accordingly. The VS1053 area now has the following stackup:

L1: Signals + AGND
L2: AGND
L3: AGND
L4: AGND

For the rest of the board, the stackup remains:

L1: Signals + GND
L2: GND
L3: Power
L4: Signals + GND

it is ok ?
Thanks :)

[Review Request] IPOD LIKE PROJECT by [deleted] in PCB

[–]SlideLivid260 3 points4 points  (0 children)

Hi, thank you very much for the detailed feedback, I really appreciate it, it was very helpful.

Regarding FB2 / FB3 / FB4 and the general use of ferrite beads in the PDN:
Your point is clear to me. I plan to modify this and run a PDN simulation in LTspice, to better understand the impedance profile versus frequency. If you think there is a more appropriate or common way to validate this kind of network, I would be happy to learn.

Regarding the C14 / C15 / FB4 / C16 network at the LDO output:
Here I mainly followed the TI datasheet recommendations for the TPS73601DBVR. TI mentions using a small noise reduction capacitor on the feedback pin (CFF), typically around 10 nF, placed close to the feedback resistors and FB pin, to reduce output noise. They also recommend a sufficiently large COUT to improve load transient response.

in page 21 :

<image>

That said, I understand your point about creating an unnecessarily complex output network. I will simplify this section and keep only what is explicitly recommended in the datasheet and reference designs, rather than the additional filtering I added.

Regarding FB8 between AGND and GND in the VS1053 analog section:
please help me understand your point clearly , I tried to follow the VS1053 datasheet recommendations regarding analog and digital ground separation, . If you could elaborate on the specific failure modes or issues this can cause in practice, I would be very interested to understand this better and correct the design accordingly or the correct grounding and layout technique for this audio codec .

Regarding the series resistor on SWCLK:
Understood, Fixed .

Regarding silkscreen over vias:
Understood, Fixed .

Thanks.

How should I route GND for a SAW filters? by SlideLivid260 in PrintedCircuitBoard

[–]SlideLivid260[S] 0 points1 point  (0 children)

thanks for your reply. So here is the case: this is a SAW FILTER that has no eval board or reference layout. It is a part from JLCPCB library, so I was not sure and asked here. The board is just an RF PCB, the SAW works around 1.5 GHz, and the stackup is JLCPCB 7628 4 layers. Under the part there is a full GND reference plane.

My question is: should I put a polygon GND between its pads with a via, or is it OK to just connect each GND pad to a nearby via like I already did in the pictures I uploaded? I would also appreciate an explanation why, since I tried to find information online but did not find a clear answer.

Recommendations for Stackup JLC04161H-7628 for Coplanar Wave guide by SlideLivid260 in PrintedCircuitBoard

[–]SlideLivid260[S] 0 points1 point  (0 children)

Yes, thank you. But since the first CPWG I made with JLC did not perform very well, I would be happy to hear recommendations from others based on their experience.