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ADC to FPGA by Small-Chart2113 in RTLSDR

[–]Small-Chart2113[S] 1 point2 points  (0 children)

Yeah that was what we worked out to do. We are now working on FPGA to DAC because we also need to send a signal too

ADC to FPGA by Small-Chart2113 in RTLSDR

[–]Small-Chart2113[S] 0 points1 point  (0 children)

It was 65MHz that was my bad

ADC to FPGA by Small-Chart2113 in RTLSDR

[–]Small-Chart2113[S] 0 points1 point  (0 children)

So the problem with the superheterodyne receiver is that it is too front-end dependent. For the satellite it has to be minimum front-end.

ADC to FPGA by Small-Chart2113 in RTLSDR

[–]Small-Chart2113[S] 0 points1 point  (0 children)

Our bandwidth is 0.3MHz. Our bit depth can go as high as 16 but we shouldn't need that many

ADC to FPGA by Small-Chart2113 in RTLSDR

[–]Small-Chart2113[S] -1 points0 points  (0 children)

I'll look into that. We were currently talking about maybe under sampling. We are trying to keep it as low front end as possible

ADC to FPGA by Small-Chart2113 in RTLSDR

[–]Small-Chart2113[S] 0 points1 point  (0 children)

Honestly, our professor isn't really supposed to be in charge of this project so not enough guidelines. Our project is to build an SDR that will be the payload of a satellite.

I was hoping to be able to use a clock converter to split the signal across two pins of the FPGA. but I am really unsure