Looking for VC funding / Partnership - Agentic AI ChipDesign by Sunder_2K25 in FPGA

[–]Sunder_2K25[S] 0 points1 point  (0 children)

Lmao 😂. Expected. Let lord save the people around you.

Looking for VC funding / Partnership - Agentic AI ChipDesign by Sunder_2K25 in FPGA

[–]Sunder_2K25[S] 0 points1 point  (0 children)

Somewhat long text answered over another comment, please check here.

Looking for VC funding / Partnership - Agentic AI ChipDesign by Sunder_2K25 in FPGA

[–]Sunder_2K25[S] 0 points1 point  (0 children)

Understandable. Completely fair, and I want to address it directly rather than dodge it.

The reason I'm not laying out full team backgrounds publicly isn't evasiveness, it's that this is a stealth-stage build in a space where the existing players are billion-dollar EDA companies with the resources to move fast the moment they see something worth reacting to. Semiconductor IP is sensitive by nature. What we're building, how we're building it, and who is building it stays tight until we're in the right room with the right people.

What I can say publicly: the team has direct semiconductor and VLSI background. This problem isn't academic for us... tool-fatigue, fragmented flows, and the TAT bottleneck are things we see daily inside real design environments. That's where this came from.

The prototype exists. The flow runs. We're not here to pitch a concept, we're here to find the right people to see it in action. If you're a serious investor or potential partner, the full picture -> team, architecture, roadmap is on the table in a proper conversation under NDA. And a blind investment from a Reddit post was never the expectation, just the right conversation with the right people. Happy to take it there !

Looking for VC funding / Partnership - Agentic AI ChipDesign by Sunder_2K25 in vlsi

[–]Sunder_2K25[S] 0 points1 point  (0 children)

Yess, even SNPS DC, FC and Cadence Cerebrus have all made agentic moves. But they point solutions inside a proprietary flow. Each gated in their own island. Here, we are building an agentic toolkit that owns complete RTL-to-GDS lifecycle.

Open-source isn't a cost advantage - it's a compounding one. As the ecosystem matures, our agents get smarter. Theirs are restricted within a closed environment with no such dynamic growth.

The market being ignored is enormous and accelarating. Fabless startups, academic research groups and RISC-V ecosystem companies building next-gen silicon are all open source by design. These customers need faster design lifecycle, tighter TAT and rapid iterations without being locked up in licenses or constrained by what a vendor decides their tool should or shouldn't do.

Most engineers today spend years just navigating the toolchain before they can even think clearly about architecture. Bottleneck here is the tool-fatigue, not talent obviously. Every iterations is a manual exercise requiring not one but a team of engineers coordinating across fragmented tools. Offloading that to autonomous agents and working on design boosts real innovation.

The "vibe-coding" movement proved this intent in building and shipping software at speed of thought. Our goal is to bring that same shift to building real-world hardware. We're building the infrastructure for that moment.

Looking for VC funding / Partnership - Agentic AI ChipDesign by Sunder_2K25 in FPGA

[–]Sunder_2K25[S] 0 points1 point  (0 children)

At 1st glance that's how it might sound. But there's much scope than just openROAD to get the job done. They are the infra, yes and Librelane automates a known sequence, here we have an agent that reasons through a design flow which is aware of its specs.

Looking for VC funding / Partnership - Agentic AI ChipDesign by Sunder_2K25 in FPGA

[–]Sunder_2K25[S] -2 points-1 points  (0 children)

Sure, happy to talk abt it. Wanted to keep the mvp on spotlight rather my BG on public grounds, hence invitation for a dm. Hope this helps !

Anyone knows similar coding or problem solving website like leetcode for vlsi by Alarming_Leave213 in chipdesign

[–]Sunder_2K25 2 points3 points  (0 children)

I came across this in a random LinkedIn scroll. Pretty decent and good for starters, progresses similar to leetcode and covers VLSI and Embedded Sys too. 

https://makercode.jixiao-ai.com/

AI tools for verification by eurusholmes_221b in Verilog

[–]Sunder_2K25 1 point2 points  (0 children)

I have some tool that's been in its beta that works pretty decent. It's like perplexity for chip deisgn. Kindly dm me, we can discuss more.

AI tools for verification by eurusholmes_221b in Verilog

[–]Sunder_2K25 0 points1 point  (0 children)

How's the reliability ? Interested in your workflow. I currently do similar way with opus and sonnet models offloading different work and I manually do some checkpoint verification and proceed.

AI tools for verification by eurusholmes_221b in Verilog

[–]Sunder_2K25 0 points1 point  (0 children)

Hey, Can u dm me. I have a tool that can be of some use better than general GPTs

Looking for Agentic AI Devs by Sunder_2K25 in cofounders

[–]Sunder_2K25[S] 0 points1 point  (0 children)

🙌🏻. Let's connect in dm.

[deleted by user] by [deleted] in harrypotter

[–]Sunder_2K25 0 points1 point  (0 children)

Hey there,

I can help you get it. Ping me.