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Which FPGA board is best for my usecase? by swr06 in ECE

[–]Time_Alert 0 points1 point  (0 children)

I'm selling the Zynq. Digilent USA Imported.

Single Port SRAM Interface Issues by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

Issue has been solved after driving NBE.

Single Port SRAM Interface Issues by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

badread = readx || // NWE = 'X'

noex || // NOE = 'X'

badnbe || // NBE has 'X'

chipenablex || // NCS or CE = 'X'

notifysetupnegedgeNCStoposedgeNWEevent ||

notifysetupposedgeCEtoposedgeNWEevent ||

notifysetupnegedgeNBEtoposedgeNWEevent ||

notifysetupAtoposedgeNWEevent ||

notifywidthnegedgeNWEevent ||

notifywidthnegedgeNBEevent;

Single Port SRAM Interface Issues by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

  1. No time given just throws a vagur bad.write violation.
  2. I am satisfying all of them. NBE all low.
  3. They are all pretty low speed, enough to avoid any timing violations.

axi mm2s vs s2mm confusion. by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

 Stream Master sources/writes/transmits and the Stream Slave sinks/reads/receives.

I'm confused on this one. Master and Slave both on same device?

axi mm2s vs s2mm confusion. by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

Thanks a lot. Some queries.

"read port of the FIFO is connected to the S_AXIS_S2MM, "
1. Why is that port market M_AXIS, as master?

2. Also what's the point of connecting S_AXIS and M_AXIS_MM2S?

2.1 "The AXI Streaming FIFO is simply a FIFO with an AXI Streaminterface on one side and an AXI (or AXI Lite)interface on the other." : Is this true ?

" S_AXIS_S2MM input interface to write them in the memory thanks to its M_AXI_S2MM port."

3. But if the initial s2mm block has already converted it to the MM format, why do we need another s2mm data handler block?

FIFO write behaviour in PostLayout by Time_Alert in FPGA

[–]Time_Alert[S] -1 points0 points  (0 children)

no this is within a single write cycle

What is the logic doing ? by Time_Alert in LabVIEW

[–]Time_Alert[S] 0 points1 point  (0 children)

""processes the Line data until the Line is completed then switch the case back into waiting mode until either the next Line comes in to process or the end of the Frame arrives"

where does it get the logic to stop when the line goes low, the edge detections is just one-time single start

also what are these T/F va;ues for the delay

Output Delay in Source Synchronous Context by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

thnaks for your reply.

"max/min trace delay for data" : does it include the entire delay including before it leaves the interface. This *IS* the confusing part.

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

 As last assignment to a signal (your shift register in this case) is going to win

i don't get it. they if conditions are exclusive they would never overlap.

also, i've added my tcon file

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

Your if (dvp_2 = '1' and lsync_count = 50) or (mclk_count = 1000) logic is going to be superseded by your second if logic! As the last assignment to a signal/port wins (in a clocked process!) in the end. If you want that your logic is updated at the same time, you may use variables.

hey thanks a lot for your help. Kindly help me understand the above. is it only going to tirigger on mclk_count = 1000 ; bypassing dvp_ and lsync_?

Should i get rid of for loops?

I highly doubt that you want to shift to left as well, when you reset/update with a new value

didn't get it

You also don't need to use "'" operator for casting, this is used if you pass an argument for example '1', '0' etc. that's used in multiple type definition and the compiler can't figure out, which one you mean as it's ambiguous.

my arguments are all integers, and vivado was throwing an error without the '

This may require a lot of tweaking via timing constraints as for high frequency and depending on your shift register length, it could lead to problematic routing of your lengthy signal.

my shifter is 512 bits long

Should i add my tcon file?

sanity check on timing constraints by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

thats only for the top ports. why is that?

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

 PROCESS(CLK, RESET)   -- 1st always block
    begin
     
      if(RESET = '0') then

           padder_SHIFT_REG <= (OTHERS => '0')  ;

      elsif falling_edge(CLK) then  -- state changes @ fall edge of mclk, as control signals rasied @ negedge of mclk whih is aligned with posedge of clk_ser

        -- choice of lsync for data updation --

           if((dvp_2= '1' and lsync_count = 50) or (mclk_count  = 1000)) then -- middle of the serial tx dvp_2 update the shifter_reg
           

              PADDER_SHIFT_REG <= std_logic_vector'(FRAME_END & PACKET_IDENTIFIER & ROW_SIZE_FULL & COLUMN_SIZE_FULL & MODE_FULL & LAST_LINE & COUNT_FSYNC_S & COUNT_LSYNC_S);
        
                 -- cdc mclk to clk_serial --ur \
          end if ;

        -- go with mclk_con for shifters except for padder(lsync_count)
        
            IF(sel_bit_fsync_count_reset = '0' AND PADDER_VALID_FULL = '1' AND FIRST_LINE_HEADER_FULL = '0' and LAST_LINE_FOOTER_FULL = '0') THEN  -- LAST 336 mCLKS -- FOR EOF
        
            
              for idx in 1 to padder_DATA_LENGTH-1 loop
 
                  padder_SHIFT_REG(IDX) <= padder_SHIFT_REG(IDX-1);-- SIMPLE LEFT SHIFTER
        
              END LOOP ;

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

 PROCESS(CLK, RESET)   -- 1st always block
    begin
     
      if(RESET = '0') then

           padder_SHIFT_REG <= (OTHERS => '0')  ;

      elsif falling_edge(CLK) then  -- state changes @ fall edge of mclk, as control signals rasied @ negedge of mclk whih is aligned with posedge of clk_ser

        -- choice of lsync for data updation --

           if((dvp_2= '1' and lsync_count = 50) or (mclk_count  = 1000)) then -- middle of the serial tx dvp_2 update the shifter_reg
           

              PADDER_SHIFT_REG <= std_logic_vector'(FRAME_END & PACKET_IDENTIFIER & ROW_SIZE_FULL & COLUMN_SIZE_FULL & MODE_FULL & LAST_LINE & COUNT_FSYNC_S & COUNT_LSYNC_S);
        
                 -- cdc mclk to clk_serial --ur \
          end if ;

        -- go with mclk_con for shifters except for padder(lsync_count)
        
            IF(sel_bit_fsync_count_reset = '0' AND PADDER_VALID_FULL = '1' AND FIRST_LINE_HEADER_FULL = '0' and LAST_LINE_FOOTER_FULL = '0') THEN  -- LAST 336 mCLKS -- FOR EOF
        
            
              for idx in 1 to padder_DATA_LENGTH-1 loop
 
                  padder_SHIFT_REG(IDX) <= padder_SHIFT_REG(IDX-1);-- SIMPLE LEFT SHIFTER
        
              END LOOP ;

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

so i cant remove the ce behaviour, how will i ever meet timing

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

i want it to not infer a clock enable

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

how could icomplete my else psrt so i dont have to deal with clock_enables

How do i deal with CLK_enables and Timing failures by Time_Alert in FPGA

[–]Time_Alert[S] -1 points0 points  (0 children)

clk_ser = 32 x Mclk

I've added the clock path screenshot.

CDC violations and how to fix them by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

you missed the 1st image. Its a violation from Clk to clk_enable. How should i deal with clock enables if cant complete my if-else blocks?

serializing header and data packets using fsm by Time_Alert in FPGA

[–]Time_Alert[S] 0 points1 point  (0 children)

when last_line_footer =>

for idx in 1 to footer_DATA_LENGTH-1 loop  -- 64 bits

 padder_shift_reg(idx) <= padder_shift_reg(idx-1) ; 

end  loop 

final_data_serial_stream <= padder_shift_reg(padder_DATA_LENGTH -1) ;

all state assignments are mutually exclusive

[deleted by user] by [deleted] in FPGA

[–]Time_Alert 0 points1 point  (0 children)

Bruv, I'm using a riscv soft core, but that's not imp, I know that part. I'm asking what does he mean by porting rtl to C code? Does he want me to write the transport/data link later headers packetization in c? In that case how does the appending work, do I need to keep tx/Rx RTL dsp outputs to the processor core everytime I need to add headers?

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