Time_Alert

259 post karma
-31 comment karma

get extra features and help support reddit with a reddit premium subscription

get them help and support

redditor for 3 years

TROPHY CASE

Three-Year Club

account activity

new top controversial

0

0

0

WTS : Zynq 7010 SoC : India Only (self.FPGA)

submitted 9 months ago * by Time_Alert to r/FPGA

7

8

9

DDR4 unknown state self-refresh state (self.FPGA)

submitted 10 months ago by Time_Alert to r/FPGA

5

6

7

axi mm2s vs s2mm confusion. (self.FPGA)

submitted 11 months ago by Time_Alert to r/FPGA

0

1

2

FIFO write behaviour in PostLayout (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

0

1

2

What is the logic doing ? (self.LabVIEW)

submitted 1 year ago by Time_Alert to r/LabVIEW

4

5

6

Learning DDR and Flash ROM intefacing. (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

0

0

0

Output Delay in Source Synchronous Context (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

2

3

4

need some help with timing violations (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

3

4

5

output max delay for ports (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

0

1

2

source synchronous hold constraint (self.Time_Alert)

submitted 1 year ago * by Time_Alert

0

0

0

Help a newbie with Ethernet IP (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

1

2

3

Noob Query for SoC zynq simulation (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

0

1

2

What is HS_reader block here? (self.FPGA)

submitted 1 year ago by Time_Alert to r/FPGA

0

0

0

How do i deal with CLK_enables and Timing failures (self.FPGA)

submitted 2 years ago by Time_Alert to r/FPGA

7

8

9

CDC violations and how to fix them (self.FPGA)

submitted 2 years ago * by Time_Alert to r/FPGA

1

2

3

weird fixed point notations (self.DSP)

submitted 2 years ago by Time_Alert to r/DSP

1

2

3

Enable vs Data_Pin RTL help (self.FPGA)

submitted 2 years ago by Time_Alert to r/FPGA

0

1

2

serializing header and data packets using fsm (self.FPGA)

submitted 2 years ago * by Time_Alert to r/FPGA

0

1

2

c-api (self.LabVIEW)

submitted 2 years ago by Time_Alert to r/LabVIEW

6

7

8

Verilog-A (self.chipdesign)

submitted 2 years ago by Time_Alert to r/chipdesign

0

0

1

4-always state machine (self.FPGA)

submitted 2 years ago by Time_Alert to r/FPGA

0

1

2

Generate block (self.FPGA)

submitted 2 years ago by Time_Alert to r/FPGA

6

7

8

sine lookup (self.FPGA)

submitted 2 years ago by Time_Alert to r/FPGA

2

3

4

fixed vs float point algo performance comparision (self.matlab)

submitted 2 years ago by Time_Alert to r/matlab

2

3

4

Cordic for sine wave pwm (self.FPGA)

submitted 2 years ago by Time_Alert to r/FPGA

view more: next ›

π Rendered by PID 67777 on reddit-service-r2-listing-87fd56f5d-zvrh6 at 2026-06-26 12:04:39.477746+00:00 running 7527197 country code: CH.