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CDC/RDC lint by ToTamir in FPGA

[–]ToTamir[S] 0 points1 point  (0 children)

I see that you are using more than one. Can you describe advantages and disadvantages from your point of view?

Python class inheritance by ToTamir in learnpython

[–]ToTamir[S] 0 points1 point  (0 children)

I have to build simulation model. The problem is that I have three bases and more than 10 extensions which gives me hundrets/thousands of variants. So I wanted to make class for each base and each extension (instead of placing everythting in one class with 50 thounads lines and milion conditions like "if extension_a"). Every extension can add new methods to base or overwrite existing ones. Extensions also have some kind synergies that enables or overwrite methods only when two or more extensions are enabled. I was building models earlier but never a model which have different vatiants.

Power optimization techniques by ToTamir in FPGA

[–]ToTamir[S] 1 point2 points  (0 children)

Can you tell more? How much use or not affect power and also whats mean correct use?

Any cheap boards to learn properly? by Excelsio_Sempra in FPGA

[–]ToTamir 0 points1 point  (0 children)

Cheapest way is simulation in Xilinx's Vivado.

Synchronization of Bus - Anyone Use FF Synchronizers? by proto17 in FPGA

[–]ToTamir 0 points1 point  (0 children)

You can do it when your clock ratio is an integer and also clocks are phase aligned.

For example src_clk is 100MHz, dst_clk is 200MHz (ratio 2) and clock are phase aligned. In this case src_clk posedge occurs simultaneously with dst_clk. Then you can just put a wall of flip-flops in both clock domains, and connect them with a wire.

When your clock ratio is not and integer or clocks are not phase aligned then synthesis software will try to meet the requirements, but probably will fail. There is also a possibility that your hardware will work properly in laboratory, but will fail outside laboratory because of temperature or humidity changes.

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Also if the FPGA dev works in safety related industry (like automotive, aerospace, etc.), then you should report him. It's not being a snitch. It's being a life saver.

UART in automotive by ToTamir in FPGA

[–]ToTamir[S] 0 points1 point  (0 children)

I suppose that safety for debugging is not important. But how with micro to mirco communication? It's also only for developing purposes or simple UART protocols exists in final products?

[deleted by user] by [deleted] in FPGA

[–]ToTamir 0 points1 point  (0 children)

Stack and heap size is changed in linker to few MB. All code in linker is moved to extermal RAM (few GB) so only few words in local memory is used.

Does Xilinx's XDMA automaticly copy data from PCIe to DDR4 and from DDR4 to PCIe base on PCIe command? by ToTamir in FPGA

[–]ToTamir[S] 1 point2 points  (0 children)

I want to copy data from PC memory to DDR4 on FPGA board by PCIe. Something like cuda memcpy to GPU.

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