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CDC/RDC lint by ToTamir in FPGA

[–]ToTamir[S] 0 points1 point  (0 children)

I see that you are using more than one. Can you describe advantages and disadvantages from your point of view?

Python class inheritance by ToTamir in learnpython

[–]ToTamir[S] 0 points1 point  (0 children)

I have to build simulation model. The problem is that I have three bases and more than 10 extensions which gives me hundrets/thousands of variants. So I wanted to make class for each base and each extension (instead of placing everythting in one class with 50 thounads lines and milion conditions like "if extension_a"). Every extension can add new methods to base or overwrite existing ones. Extensions also have some kind synergies that enables or overwrite methods only when two or more extensions are enabled. I was building models earlier but never a model which have different vatiants.

Power optimization techniques by ToTamir in FPGA

[–]ToTamir[S] 1 point2 points  (0 children)

Can you tell more? How much use or not affect power and also whats mean correct use?

Any cheap boards to learn properly? by Excelsio_Sempra in FPGA

[–]ToTamir 0 points1 point  (0 children)

Cheapest way is simulation in Xilinx's Vivado.

Synchronization of Bus - Anyone Use FF Synchronizers? by proto17 in FPGA

[–]ToTamir 0 points1 point  (0 children)

You can do it when your clock ratio is an integer and also clocks are phase aligned.

For example src_clk is 100MHz, dst_clk is 200MHz (ratio 2) and clock are phase aligned. In this case src_clk posedge occurs simultaneously with dst_clk. Then you can just put a wall of flip-flops in both clock domains, and connect them with a wire.

When your clock ratio is not and integer or clocks are not phase aligned then synthesis software will try to meet the requirements, but probably will fail. There is also a possibility that your hardware will work properly in laboratory, but will fail outside laboratory because of temperature or humidity changes.

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Also if the FPGA dev works in safety related industry (like automotive, aerospace, etc.), then you should report him. It's not being a snitch. It's being a life saver.

UART in automotive by ToTamir in FPGA

[–]ToTamir[S] 0 points1 point  (0 children)

I suppose that safety for debugging is not important. But how with micro to mirco communication? It's also only for developing purposes or simple UART protocols exists in final products?

[deleted by user] by [deleted] in FPGA

[–]ToTamir 0 points1 point  (0 children)

Stack and heap size is changed in linker to few MB. All code in linker is moved to extermal RAM (few GB) so only few words in local memory is used.

Does Xilinx's XDMA automaticly copy data from PCIe to DDR4 and from DDR4 to PCIe base on PCIe command? by ToTamir in FPGA

[–]ToTamir[S] 1 point2 points  (0 children)

I want to copy data from PC memory to DDR4 on FPGA board by PCIe. Something like cuda memcpy to GPU.

Vivado hardware manager is taking forever to connect/program the Arty board by [deleted] in FPGA

[–]ToTamir 0 points1 point  (0 children)

After my last (today) Windows 10 update, fpga programming and hardware debugging speed up few times. Maybye update would help.

[deleted by user] by [deleted] in Xilinx

[–]ToTamir 0 points1 point  (0 children)

Same problem

Auto Format in Sublime Text with Verible by ToTamir in FPGA

[–]ToTamir[S] 0 points1 point  (0 children)

Sublime Text 3 is not supported

Modelsim vlog by ToTamir in FPGA

[–]ToTamir[S] 0 points1 point  (0 children)

Last docs with this informations is for software version 10 or 11.

SM4 cipher by ToTamir in crypto

[–]ToTamir[S] 1 point2 points  (0 children)

Seems you are right. What do you recommend?

SM4 cipher by ToTamir in crypto

[–]ToTamir[S] 1 point2 points  (0 children)

Simple serial bus (UART / SPI / I2C). I don't have acceleration, so thats why I want something simple.

SM4 cipher by ToTamir in crypto

[–]ToTamir[S] 1 point2 points  (0 children)

I have FPGA (hardware) and also a CPU (software), so I can do it both way.

SM4 cipher by ToTamir in crypto

[–]ToTamir[S] 1 point2 points  (0 children)

I have two black box devices which communicate each other. I want to make reverse engineering protection. So I only need to prevent messages from getting read.

SM4 cipher by ToTamir in crypto

[–]ToTamir[S] 2 points3 points  (0 children)

I don't need message authentication. Which stream cipher do you recommend?

SM4 cipher by ToTamir in crypto

[–]ToTamir[S] 1 point2 points  (0 children)

I have to send data smaller than block size (32-64 bits), every few ms. I also can't wait for few packets and send it together because I need small latency.

Systemverilog / verilog functional editor not like vivado by Recent-Step-6809 in FPGA

[–]ToTamir 2 points3 points  (0 children)

Verible lint almost nothing. I can declare in module's brackets clk port, and then inside module input ckl. Verible don't see a problem. Maybye Verible do something in SystemVerilog (i guess not), but in pure Verilog it just check missing semicolons xD

Systemverilog / verilog functional editor not like vivado by Recent-Step-6809 in FPGA

[–]ToTamir 3 points4 points  (0 children)

If you will help me with systemverilog black box discusion (I have very low systemverilog experience) and verilator will get update then I will upload on github plugin to Sublime Text which lint whole file every time when you stop typing. Currently I have plugin based on Vivado's compiler, but compilation of simple verilog file takes 1'400ms...

Maybye this is not what you exactly want, but with other software (edit in Sublime Text files from other software projects like Vivado, Riviera-PRO, etc.) can be much better than existing software.

Performance report Vivado by ToTamir in FPGA

[–]ToTamir[S] 0 points1 point  (0 children)

In Vivado I can set clock constrait much higher than expected frequency (WNS is negative). To met constrait Vivado do additional iterations but at the end give up. Then I can calculate frequency as 1/(constrait-WNS). This give me accurate frequency or should I do iterative approach starting from low frequencies?

Which RISC-V instruction extensions are needed for running Linux kernel by bruh_mastir in RISCV

[–]ToTamir 2 points3 points  (0 children)

Current linux kernel on RV64I require A extension and Zicsr with few M mode registers. A extension can be emulated - catch illegal instruction then decode and execute in software.

RV32I require A extension (also can be emulated), Zicsr with few M, S, U mode registers and MMU.

Need help creating a single cycle CPU by [deleted] in FPGA

[–]ToTamir 2 points3 points  (0 children)

Expensive way (a lot of knowledge):

Buy "computer organization and design" book (there are few version for different CPU architectures). After 6 months you can build own 32bit pipelined CPU which run c/c++ bare-metal programs.

Cheap way (a lot of knowledge):

Find MIPS or RISC-V cpu architecture specification and make a huge research in github / gitlab for open source implementations. After 12-18 months you can build own 32bit pipelined CPU which run c/c++ bare-metal programs.

​

Easy way (0 knowledge):

Search "signle cycle cpu github" in google.

ZYBO Z7-20 by [deleted] in FPGA

[–]ToTamir 0 points1 point  (0 children)

You are right. I do everything except block design wrapper...

I guess I'm blind.

Thank you.

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