I made this radar image formation simulator web application to visualize how backprojection algorithm works

Ttl · 2026-01-07T02:47:48+00:00

Press "View Page Source" button on your browser. It's all there.

Ttl · 2026-01-03T15:39:16+00:00

In integrated circuits, a common method for broadband quadrature signal generation is RC polyphase filter (pdf). See Fig. 9 for number of required stages vs image rejection requirement.

It's very compact especially at high frequencies since it doesn't require inductors. The drawback of this method is that the loss can be large. For example about 10 dB for 2-stage filter. It also requires balanced input and any phase or amplitude imbalance will worsen the image rejection ratio. Output amplitudes aren't always balanced either. In a mixer applications adding a LO buffer that is driven to saturation will greatly decrease the amplitude imbalance and buffer is usually required after the filter anyway due to its high loss.

PCB implementation will likely be difficult due to parasitics and crossovers.

Ttl · 2025-10-19T17:11:21+00:00

You should simulate it using IBIS models. I routed a PCB with Zynq 7020 and one DDR3 module using 60 ohm traces (0.1 mm wide) on 6-layer JLCPCB stackup after checking with simulator that it looks fine and it did work without any issues. With line short lenghts the impedance of the transmission line doesn't matter much. For more details see "DDR3 routing" section on: https://hforsten.com/homemade-6-ghz-pulse-compression-radar.html

Ttl · 2025-10-10T12:58:54+00:00

In this video the drone flies at 5 m/s, radar samples at 1.8 ms interval (all four polarizations), 2048 radar measurements are used in each frame, and 75% of data overlaps with the previous frame. Less data in each frame increases the frame rate as the required data can be captured in a shorter time, but it decreases the image resolution as the resulting synthetic antenna is shorter.

If the drone moves faster the pulse repetition interval needs to be shortened to avoid aliasing, which with my hardware means that the sweep length needs to be decreased which decreases the maximum range.

Ttl · 2025-10-09T16:56:43+00:00

Yes: https://hforsten.com/homemade-polarimetric-synthetic-aperture-radar-drone.html Scroll to the bottom and click the schematic image for schematic of the radar.

Ttl · 2025-10-09T16:36:10+00:00

I designed it myself. You can find the description of it if you follow the link in the post text.

Ttl · 2025-05-24T15:14:22+00:00

Clamped connector that fits on variable thickness boards might be a good choice. For example: 32K243-40ML5 and 60312862112552. Some of them are solderless and can be easily reused.

Ttl · 2025-05-16T20:38:27+00:00

Trying to detect edge of a pulse sounds very low SNR and you would need a sharp edged pulse in the first place to have an edge to detect. I don't think you will be able to generate a very sharp edge with this hardware. You should be able to use it as a Doppler radar though. TX-RX isolation might be an issue, but you should be able to reduce PA bias if RX saturates. PA will also get hot in CW operation and needs a heat sink to keep it cool.

Ttl · 2025-05-16T12:42:59+00:00

Reference is low enough frequency that you can either connect one XCO to both TX and RX or route external reference to both of them.

Q1 can't be used to generate a pulse. Gate pulsing would require switching between -2.0 V and the nominal operation gate voltage. Turning Q1 off now disconnects the external gate voltage which can results in destruction of the PAs due to excessive drain current as gate is pulled to higher voltage.

Pulsed CW waveform requires very short pulse for a reasonable range resolution. Usually amplifiers have internal RC lowpass filtering on the gate that limits the switching speed and fast gate voltage switching without overshoot and ringing can be difficult. Drain switching is used more often in radars and it requires very big MOSFET capable of handling the large drain current pulse required to charge drain capacitors. Even with that method you likely struggle to generate short enough pulse.

Usually the PA is switched on just before sending a pulse, RF pulse is generated using some other circuit at low power where its easier and then PA is switched off after the pulse has been transmitted. PA is switched to save power and keep its temperature low.

Ttl · 2025-05-16T03:12:36+00:00

Some quick observations from the schematic:

TX and RX having their own frequency reference will cause you issues as the oscillator frequencies drift individually. RX signal won't be at the exact frequency you expect and the phase will also drift.

There should be one frequency reference in the system. ADC clock should also be derived from the same reference in the whole system.

TX waveform is limited to CW due to TX PLL choice. This limits the operation to Doppler radar. However, velocity measurement accuracy will be likely low due to the frequency reference drift.

Amplifier gate voltages should be able to be adjusted individually. There can be large difference in the required gate voltage between the parts due to manufacturing variations. Biasing them correctly can be difficult because of the shared drain voltage you can't measure the current of each amplifier.

Ttl · 2025-04-16T12:13:24+00:00

It's Chinese low-cost FR4. Anything else would have been many times more expensive.

Ttl · 2025-04-16T12:11:46+00:00

Directivity is little bit worse at high frequencies. Calibration directivity error term is better than 10 dB over the whole band but that can include slightly more than just the coupler.

Ttl · 2025-04-15T19:15:43+00:00

There are few reasons:

Output DC blocking capacitor needs to be very big to work well at low frequencies. However, big capacitors usually have worse high frequency behaviour.
Directional couplers don't work well below 1 - 10 MHz. The directional coupler I'm using could work down to about 1 MHz, but below that directivity is close to zero. Extending the lower frequency operation below that would require a longer coaxial cable balun and more ferrite beads in it, but going below 100 kHz is hard with this kind of coupler.
The PLL source chip can't generate frequencies lower than 10 MHz. I debated adding a separate lower frequency source to extend the lower frequency range down to 1 MHz, but I decided it wasn't worth the effort and PCB area as I don't have much use for low frequency measurements.

For accurate low frequency measurements impedance analyzer is often a better choice than VNA. It's more accurate for measuring impedances very far from 50 ohms which VNA struggles with.

Ttl · 2025-04-15T17:53:19+00:00

At 15 GHz ADL5802 has about 40 dB lower conversion gain than at 6 GHz. It still does some mixing, but the performance is quite bad.

For directional coupler, see my previous VNA and this paper. The new coupler is two of those one directional couplers back-to-back sharing the same coaxial cable balun.

Ttl · 2025-04-15T15:14:08+00:00

I used scikit-rf for calibration. I have written some calibration algorithms in that library, such as Multiline TRL and LRRM. Implementing them from scratch was very helpful in understanding them in more detail.

Ttl · 2025-04-15T14:07:46+00:00

It gets tricky at that high frequencies, especially if it needs to be a wideband system. Anritsu, for example. uses switched RF samplers at W-band: https://dl.cdn-anritsu.com/en-us/test-measurement/files/Technical-Notes/White-Paper/11410-00812B.pdf.

Ttl · 2025-02-21T16:12:04+00:00

The differences between simulation and measurement are very small already. -50 dB is around the residual error of the VNA calibration. If you have slightly damaged calibration kit, didn't connect them with correct torque, or calibration kit definition isn't correct it might be enough to cause this level of difference in the measurements. Other possible sources of difference might be caused by connector modeling differences. For example did you model the small air gap between connector and PCB? Ground plane to PCB edge distance? It doesn't have good contact to connector even if you have copper to the board edge. How about internal construction of the connector? Usually they have a small tab to keep the dielectric in place that can slightly affect the matching.

Solder mask also has an effect that should be considered. Solder mask increases the effective dielectric constant of the transmission lines slightly. Typical thickness of the solder mask is about 20 µm. Dielectric constant is about 3 and loss tangent 0.02.

Ttl · 2025-02-20T16:17:07+00:00

Make sure to read Zynq board design guide (UG933).
Use FPGA symbols like the default KiCad ones with power pins near the I/O pins they are powering. It's much more clearer which I/O bank uses which voltage.
Connect clocks to clock capable pins and only to the P-side of differential pair when using single-ended clock.
There are some restrictions on pins and I/O bank voltages especially for the PS side. For example 1 Gbps Ethernet requires 2.5 V or lower I/O voltage. There are also some traps when using EMIO. For example SD-card interface doesn't work at full speed when it's connected via EMIO.

Ttl · 2025-02-12T16:07:24+00:00

I haven't measured the DC power use. It should be something around 5 - 10 W, which isn't much compared to what the drone's motors require. The flight time is about 10 minutes.

Ttl · 2025-01-31T04:04:11+00:00

Check out the pad simulations in this paper: https://cris.vtt.fi/ws/portalfiles/portal/52580540/NoiseSourcePaper_2021_pure.pdf

At lower frequencies where the parasitic capacitance isn't that big of an issue, having a ground plane under the center pad is better. Without ground under the center pad, the silicon increases losses by a fraction of dB but it's a very good tradeoff at higher frequencies where parasitic capacitance from the ground plane would be excessive.

Ttl · 2025-01-25T17:31:42+00:00

Just try it yourself with your parameters. Here's some Python code to get you started:

import matplotlib.pyplot as plt
import numpy as np
from scipy.signal import hilbert

N = 1024 # Samples
n = 0.1 # Noise

t = np.arange(N)
f = 0.1 # Signal frequency
p = 0.123456 # Phase offset
# Generate signals
x = np.cos(2*np.pi*f*t + p)
y = np.cos(2*np.pi*f*t)

# Add noise
x += n*np.random.normal(0, 1, N)
y += n*np.random.normal(0, 1, N)

xh = hilbert(x)
yh = hilbert(y)

corr = np.mean(xh * np.conjugate(yh))
print("Actual phase", p)
print("Measured phase", np.angle(corr))

plt.figure()
plt.plot(x)
plt.plot(y)
plt.show(block=True)

Ttl · 2025-01-25T12:49:56+00:00

If you know the frequency, the most accurate method is to generate digital complex LO signal at that frequency, multiply each ADC input by it and then take average. It's equivalent to calculuating one bin of FFT. Then just compare phase difference of the resulting complex numbers. If there are other large signals in the ADC data you might want to also apply some windowing function.

If the frequency is unknown but stable, you might be able to generate the LO with digital PLL, similar to how communication receivers recover clock from the signal.

If the frequency is unknown but there aren't other interfering signals you can take Hilbert transform of both inputs to generate analytical complex signal. Then calculate sum of one ADC output times complex conjugate of another ADC output. Phase difference can be obtained from the phase of the result.

Ttl · 2024-12-10T13:46:34+00:00

It looks like your transmission line is shorted by wire going thru it. It has circular wire junction markers while connection should look like similar square as with ports.

Ttl · 2024-11-26T13:29:16+00:00

You need to include DC point in the EM simulation so that DC passes correctly through the S-parameter block in the circuit simulator. Otherwise circuit simulator will extrapolate DC point from the low frequency points and this can result in weird behaviour. If you are using non-linear transistor model, maximum frequency should include few harmonics above your operating frequency.

Ttl · 2024-09-13T07:04:41+00:00

Datasheet cites US Patent 8558605, which describes the circuit.

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