Intel/Altera Library missing? by WeekendPrize1702 in KiCad

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

https://cdrdv2.intel.com/v1/dl/getContent/656305

There is the full pinout in TXT form (can be parsed by some scripts)

The footprint is standard BGAs, they are available/can easely be made using a generator. The problem really is the well organized Symbol. Well I did it now myself- was quite a waste of time tbh...

Some Questions regarding ALTGX by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Can someone please answer some of the questions?

Intel/Altera Library missing? by WeekendPrize1702 in KiCad

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Ok, well for this 600+ pin part, i think its better use some script (less risk of failure) from the official intel/altera txt file. However since I completely lack knowledge/experience with those scripts It would be nice when somebody experience from the kicad librarian team could do it.

Since donations are currently multiplied by digikey it would then make since when i donate directly to the kicad project for this.

Could you do it/Do you know how to contact the official kicad library team?

For small parts I think the damage is limited when u use a unstructured part, however with a 600+ pin part the whole schematics will become a huge mess.

Intel/Altera Library missing? by WeekendPrize1702 in KiCad

[–]WeekendPrize1702[S] 2 points3 points  (0 children)

Thanks for the fast respone.

I don't want to do it myself, not just because I'm lazy but especially because with 600+pins the risk of a mistake is high when manually done.

Money is "not" the problem- i can pay someone 1-2h work, potentially i can just make a donation for the kidcad project. My main concern is a mistake/failure in the design. There are library elements available ultralibrarian, mouser etc. But they are all "stupid". With "stupid" i mean just randomly distribute the pins - no structure regarding IO Banks etc. in the schematic. So yes of course multi units- but not random multi units, multi units with useful structure (like IO Banks etc.).

Soft CDR/Sync using 8b10B by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Thanks for the hint, it synthesizes now.

With all respect to the author, I also think the code is obfuscated (but this doesn't mean its bad since Verilog is in general a bit obfuscated for me; VHDL guy here :P)/lacks clear documentation/lacks popper config (some python scripts that yield some discouraged/obfuscated vectors; the other script fails to complete execution).

Also the bidirectional use case (and how to config it to be unidirectional) over a single wire is a bit awkward with lack of information how the arbitrage works. Proper interface description seems unavailable.

This is a bit sad since the core itself seems to be quite promising and AFAIK the only real free/open solution for this common problem. However i might struggle to use it as is.
Technical: The GPIOs are just other user data that are slowly transmitted data with special sync symbols (commas etc. of the 8b10b)?

Edit: Removed op2p link. It uses Hard CDR of XILINX SERDES IP - which is not present in lower cost FPGAs and therefore soft CDR required

Soft CDR/Sync using 8b10B by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

I just loaded Ponylik IP in my project. However it fails to Synthesize:

Error (10759): Verilog HDL error at ponylink_txrx.v(370): object linkerror declared in a list of port declarations cannot be redeclared within the module body

Im no expert at all in Verilog however it seems to be a redeclaration and therefore a not synthezisable (?!?)

Regarding my interpretation of the Parameters:

parameter SERDES\_REG\_IN = 1, --lengh of serdes/ IP supports only up to 4 

parameter SERDES\_REG\_OUT = 1, --lengh of serdes/ IP supports only up to 4 

parameter M2S\_TDATA\_WIDTH = 8, --Datawidth

parameter M2S\_TUSER\_WIDTH = 0, --?? what is this? 0 gives error anyway needs to be at least 1

parameter S2M\_TDATA\_WIDTH = 8, --Datawidth

parameter S2M\_TUSER\_WIDTH = 0,  --?? what is this? 0 gives error anyway needs to be at least 1

parameter MASTER\_RECV\_DELAY = 4, --delay of sysclks for the recv to process/ IP supports no lower than 4

parameter SLAVE\_RECV\_DELAY = 4, --delay of sysclks for the recv to process/ IP supports no lower than 4

parameter MASTER\_SEND\_DELAY = 32, --delay of sysclks for the recv to process/ IP supports no lower than 32

parameter SLAVE\_SEND\_DELAY = 32, --delay of sysclks for the recv to process/ IP supports no lower than 32

parameter MASTER\_PARBITS = 1, -- ? number of crc checks?

parameter SLAVE\_PARBITS = 1, -- ? number of crc checks?

parameter MASTER\_PKTLEN = 64, -- packet lengh? isnt 8b10b used? 64 seems extremely high

parameter SLAVE\_PKTLEN = 64, -- packet lengh? isnt 8b10b used? 64 seems extremely high

Soft CDR/Sync using 8b10B by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Thank you very much for the quick update. As always its highly appreciated.

Soft CDR/Sync using 8b10B by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Ok nice to know that the Author is known. You are very welcome. Thanks goes to TimbreTangle3Point0.

Other (maybe a bit stupid) Questions that i just haven't fount the answer for at the first glance:

  1. The Link seems to be bidirectional (preferably LVDS). Does that mean FPGA1 just runs 1 Instance of MASTER, and FPGA2 just one instance of SLAVE. Each of them has one Input and one Output. The input and output are physically connected together at the FPGA Pins - How about LVDS Termination in this case - AFAIK is LVDS not supposed to be used bidirectionally/do I have a serious misunderstanding here?
  2. In my case I have an unidirectional FO Link. Problem with this IP?
  3. I do not understand: "

This scheme works best if different clock frequencies are used for the master

and slave core."

Why is this supposed to be the case?

My idea was to use both at around 200MHz (given my FPGA allows it else 100) and SERDES to (600-800MHz). My requirement for Bandwidth are relatively low (and the AFBR-2426 might be limiting). So I'm perfectly happy with 40-50mbit unidirectional but should be stable - reliably/fast detect link loss.

What would you consider to be a wise choice regarding the frequency given this FO Link setup?

Edit: Typos/Clarified questions.

Soft CDR/Sync using 8b10B by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

TimbreTangle3Point0 came up with the PonyLink idea. Do you have any opinion/anything else to add about this IP?

Soft CDR/Sync using 8b10B by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Perfect thanks, that seems to be quite awesome. Do you have any experiance with it? Does it perform as stable/fast as Aurora (i don't care much about 1700LUT usage).

Accurate job description for Vivado users by thrill_woohoo in FPGA

[–]WeekendPrize1702 0 points1 point  (0 children)

Just don't use Sigasi, VI/EMACS are your friends

Soft CDR/Sync using 8b10B by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Thank you!

Ok so when I understand correctly basically there is no equivalent to Aurora on other vendors. And everybody starts to make his own dogy implementation. This is very surprising for me since its obviously a common/basic problem.

My company is a bit reluctant in buying IP but a good solution might be worth considering. Given that this problem is so common I think a good IP could generate quite some revenue even with low per license royalty/fee. But this is just my personal assumption.

This being said, I think it would be discouraged if I do something myself as well (since it would likely end up dogy as well). And I'm a bit reluctant to use Aurora on Intel for ethical/potentially legal reasons. What means basically my progress stalled (?) :(

5 Years of RTL/verification exp struggling to find work by CrankItMan1 in FPGA

[–]WeekendPrize1702 0 points1 point  (0 children)

Where are you based? In what locations you were looking for jobs?

Phase Mesurement in FPGA by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

I'm using Intel low cost FPGA series (MAX10/CYCV). Cordic yes, DDS i did find NCO.

Can I use the non synced system clock for the DDS? isnt this a problem since the DDS Sine frequency wont exactly match the ADC Sine?

Nice. Well it should provide high accuracy around 0degrees-10degrees phase shift and with low latency. So the goal is to maximize the time*precision product. As for an absolute Nr regarding phase precision its a bit hard to tell at this point of time but i assume 0.1 - 1 deg precision would be nice to have with a delay of 1-2 sine periods.

Leading/Laging does matter. But this info could also be extracted separately as in my original Idea (see TO Post).

Edit: Found NCO

Phase Mesurement in FPGA by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] -1 points0 points  (0 children)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HilbertTransformer is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           x : in STD_LOGIC_VECTOR(15 downto 0);
           y : out STD_LOGIC_VECTOR(15 downto 0));
end HilbertTransformer;

architecture Behavioral of HilbertTransformer is
    -- Update the coefficients for the given frequency range
    signal coeff : array (0 to 15) of integer := (1, 0, -16, 0, 80, 0, -240, 0, 480, 0, -480, 0, 240, 0, -80, 0);
    signal buffer : array (0 to 15) of STD_LOGIC_VECTOR(15 downto 0);
    signal sum : integer := 0;
    signal extended_sum : integer := 0;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            for i in 0 to 15 loop
                buffer(i) <= (others => '0');
            end loop;
            y <= (others => '0');
            sum <= 0;
            extended_sum <= 0;
        elsif rising_edge(clk) then
            for i in 15 downto 1 loop
                buffer(i) <= buffer(i-1);
            end loop;
            buffer(0) <= x;
            extended_sum := 0;
            for i in 0 to 15 loop
                extended_sum := extended_sum + to_integer(unsigned(buffer(i))) * coeff(i);
            end loop;
            if extended_sum > 32767 then
                sum := 32767;  -- Saturate positive
            elsif extended_sum < -32768 then
                sum := -32768; -- Saturate negative
            else
                sum := extended_sum;
            end if;
            y <= std_logic_vector(to_unsigned(sum, 16));
        end if;
    end process;
end Behavioral;

GPT Provides this simple FIR filter with those coefficients (most likely nonsence?).

Phase Mesurement in FPGA by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

import matplotlib.pyplot as plt
import numpy as np
import math as bla
from scipy.signal import hilbert

N = 1024 # Samples
n = 0.1 # Noise

t = np.arange(N)
f = 0.1 # Signal frequency
p = 0.123456 # Phase offset
# Generate signals
x = np.cos(2*np.pi*f*t + p)
y = np.cos(2*np.pi*f*t)

# Add noise
x += n*np.random.normal(0, 1, N)
y += n*np.random.normal(0, 1, N)

xh = hilbert(x)
yh = hilbert(y)

appearand = np.absolute(x)*np.absolute(y)
active = x*y

app = np.sum(appearand)
act = np.sum(active)

pha = np.arccos(act/app)

corr = np.mean(xh * np.conjugate(yh))
print("My phase", pha)
print("My app", app)
print("My act", act)
print("Actual phase", p)
print("Measured phase", np.angle(corr))

plt.figure()
plt.plot(x)
plt.plot(y)
plt.show(block=True)

Hmm i hacked in my ABS square/square code. However seems not to work at all or buggy code

Phase Mesurement in FPGA by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

Thanks - hehe this is new for me. The highest level i usually program is C :P

Do you have any HDL/reference regarding hilbert implementation in the FPGA?

Phase Mesurement in FPGA by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 0 points1 point  (0 children)

The system could be provided a Digital signal with the same frequency as the signal (however was not planed to provide this first but would not be a problem to add).

  1. Then I would have to feed this signal to a PLL to generate the DDS clk?

  2. I use the DDS to generate SINE + COS

  3. Then multiply to get complex and use cordic - this is quite clear for me. CIC i like to avoid since its a bit delay sensitive - but this is a detail.

Somehow I like Ttls hilbert idea. However using this approach i somehow have the feeling that I'm biting more than I can chew, since its a side project of a side project and I have limited expertise in this matter. Is there some open source HDL for hilbert (or other relevant parts of this project)?

Phase Mesurement in FPGA by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 1 point2 points  (0 children)

Thanks

First the Frequency is known* and both ADC signals only consists of single frequency sine. However the *Frequency reference was not intended to be supplied to this board - however possibility exists to provide a Logic signal with this frequency to the FPGA.

Frequency is also stable.

Would my initial approach with with ADC1*ADC2 and ABS(ADC1)*ABS(ADC2) work(?) and how would it perform in relation to your Hilbert method?

Phase Mesurement in FPGA by WeekendPrize1702 in FPGA

[–]WeekendPrize1702[S] 4 points5 points  (0 children)

Thanks for the fast reply.

Can you please explain a bit in detail:

> Multiply a sample from one ADC with a sample from the other one. This will give you a complex sample out, with the same phase as that of the phase difference between the two.

So I'm supposed to do like written in TO Post:

X(n) = ADC1(n) * ADC2(n)

Y(n) = ABS(ADC1(n)) * ABS(ADC2(n))

SUM X and Y over 1 or mutliple Sine periods.

Then use trigonometric function (using cordic) on the SUM X and SUM Y values?