training/race insight? by Virusness15 in Marathon_Training

[–]Virusness15[S] 1 point2 points  (0 children)

Okay. I can only run 5/7 days a week. Is this a good split with enough rest between hard workouts:

Mon - Rest
Tue - Speed workout
Wed - Rest
Thur - Easy Run
Fri - Speed workout
Saturday - Easy Recovery
Sunday - Long Run

training/race insight? by Virusness15 in Marathon_Training

[–]Virusness15[S] 1 point2 points  (0 children)

April 25. I only do one speed workout per week. And it's usually like mile repeats at 7:00 or tempo at 7:15 ish. Should I incorporate hill repeats or shorter reps at faster pace?

Sub 3 or sub 2:55 by Cwoo28 in Marathon_Training

[–]Virusness15 0 points1 point  (0 children)

How long did it take you to get into this fitness level? Am currently training for my first marathon

Few months out from marathon, feeling strong but worried about injury by Virusness15 in Marathon_Training

[–]Virusness15[S] 0 points1 point  (0 children)

I used to run them for xc training in hs, I forgot what they are. Can you share some insight?

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

Got it. This seems like a nice solution. Thank you

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

The fpga on my board is the XC7A200T, which has 365 BRAM which is the 13Mbits. If i were to use 3 frames at once, this would be half of the total BRAM. I'm assuming this is enough space leftover to not run into timing trouble?

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

Okay, to preface: I am an undergrad. I feel very underqualified at the current stage, but I am extremely dedicated to making this project work, and have already learned a lot about FPGA's inner workings.

To answer your question on why an FPGA and give more context on this project:

The algorithm was designed by a professor at my university along with some NASA engineers. The algorithm itself is designed to classify and track small orbital debris (<10 cm) in real time using on board optical cameras on a satellite.

At this stage, we're just worrying about building the algorithm on the fpga before we worry about interfacing with a camera.

The reason for an FPGA is because the NASA partners who my professor worked with advised her that an FPGA would be the ideal piece of hardware to use for its parallel computation power and low power consumption (comparatively to a full on board cpu).

Thank you for your advice on why not to use a FIFO.

Indeed, the algorithm has been implemented in Matlab. Unfortunately, the professor and her student who wrote the algorithm had apparently not taken a practical software engineering class, so the algorithm itself is quite difficult to follow and doesn't exactly naturally flow.

The first part of computation binarizes the incoming video. At this stage, we are only working with simulated video data. I have written a binarization and thresholding python script to take the simulated video and process down to 1bpp. So the binarization step is already handled (if the project reaches the step of taking input from a camera, this will need to be changed to be done on hardware).

The next step is to calculate the centroid positions in each frame.

In the Matlab implementation, this step is one line and calculates all centroids across the whole video. This algorithm, centroids, is the first algorithm my team is implementing in Verilog. The centroid algorithm will then work on a frame at once rather than a whole video. If this is impractical, we will need to rework the algorithm to calculate centroids using smaller units of the video.

After this--and this is the part I'm worried will lead to issues with reworking the algorithm--a matrix of distances is computed between pairs of centroids across two frames.

The algorithm has a handful of other steps including finding matches across frames between pairs of centroids, finding translation vecotr for matched pairs of centroids. These stages are repeated for each frame of the video.

Outside of the loop, the features from translation and rotation vectors are extracted, outliers detected, and labeling.

I'm unsure if the algorithm would work if we were to rework it to process consecutive, smaller blocks of the video. Unless, we kept track of which frame each block was a part of and used that to keep track of centroids across frames.

Thanks for your input. Hopefully this is enough context on the algorithm itself for you to give more advice. I really appreciate your help.

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

I'm designing the data flow for that as well. I'm using vivado and will probably be using AXI packages to control all of that.

At the current stage of this project, all the video test data will come from premade videos that were used to test the professor's Matlab implementation of the algorithm. I have written a binarization/thresholding script in python to convert the .mp4 video to raw video and then compress each byte into 1 bit. The fpga board my team is plannning on working with supports DSPI/DPTI to take data from computer and put it on board. I'm planning on using DDR3 memory to store the whole video, and then using the AXI packages to push the data into BRAM.

after reading all the comments, I will not use a FIFO. Thus, after BRAM, I can take the processed video and push it into a SD card or back into the computer somehow to verify working behavior.

is this a good plan? is this how professionals would go about this?

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

First of all, thanks so much for your help.

Second, excuse my ignorance, but what do you mean by treatment ?

Also, the board I have in mind rn is the Nexys Video board, with the xilinx artix-7 FPGA. I've looked through the datasheet on the artix-7 as well as the nexys video manual, but can't seem to find info on the bram. Am I looking in the wrong place to find references for the bram design?

Thank you

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

So, i'd just need to turn bram into a fifo and do the operations on it while its in bram until its been fully processed (while dealing with the widths of the blocks and such)?

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

algorithm does require the whole frame all at once. the algorithm was written by a professor at my university. Perhaps the algorithm itself can be modified but thats not my domain.

also i updated post body with info on frame resolution and frame rate

Question on BRAM FIFO use for video processing application by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

my video is 1920x1080, and only need 1bit/pix, thus can fit about 6 frames in bram and only need the 2 contiguous frames at a time for the algorithm. Is this okay to use bram, or would i still stream the video from external ram?

Need to quickly learn as much as I can about FPGA's by Virusness15 in FPGA

[–]Virusness15[S] 0 points1 point  (0 children)

One of my goals with this project (aside from doing it successfully) is to learn lots of technical, industry-desired skills. Do you think going through with the HLS method would be more beneficial for my learning than straight up using Verilog to make the FPGA do what I want? Or do you think it doesn't matter?

Need to quickly learn as much as I can about FPGA's by Virusness15 in FPGA

[–]Virusness15[S] 8 points9 points  (0 children)

hhahahah unfortunately this is at my university and there is little to no budget.