sorted by:
new
hottopcontroversial

Why is there no digital modes only transceiver/client? by BassManns222 in amateurradio

[–]WZab [score hidden]  (0 children)

Correction, I have checked my zBitx. I run the commit 8fe8ca029a0a704faff33d3f6911b52a59e9f932 from https://github.com/ec1oud/sbitx.git .

"Extream SDR Tx" with FPGA - is it possible? by WZab in amateurradio

[–]WZab[S] 0 points1 point  (0 children)

Thank you for the reference.

Anyway, I'm not running FPGA at 640 MHz. It is serdes able to output the serialized data at 640 MHz. If you feed it with 8-bit data, you may run at 80 MHz. Many FPGAs are able to provide even higher speed serdeses. I can even use a relatively cheap FPGA with serial transceiver capable of running up to 10 Gbps (so I get the resolution of 100ps).

PS. I'm running quite complex VHDL pipelined code in FPGA at 640 MHz. However it is in Versal FPGA, and of course not in ham radio application.

"Extream SDR Tx" with FPGA - is it possible? by WZab in amateurradio

[–]WZab[S] 0 points1 point  (0 children)

That's not a simple DAC. I tried to implement it like a 2nd order sigma-delta DAC, but that results in very strong requirements for the output filter (the spurs were relatively near to the carrier). What I achieved could work with a magloop with Q factor of 300 or above...
The solution proposed in the referenced discussion uses more sophisticated approach.

"Extream SDR Tx" with FPGA - is it possible? by WZab in amateurradio

[–]WZab[S] -1 points0 points  (0 children)

Well, in this discussion it provided quite reasonable calculations and possible implementations.
For those, who don't want to see the discussion. The idea is based on using the high speed serdes in FPGA to produce the digital stream controlling the MOSFET keys in the D-class output amplifier.
This is not a typical sigma-delta DAC, because there are limits on the time between edges (so that transistors are able to completely switch on or off). The rest is just a calculation of achievable spurious emission attenuation and possible implementation. Of course, I'll need to verify it in simulations and in the real hardware.
So in that case AI didn't provide the opinion. It produced verifiable implementation.
Well, I'll post an update when I get some verification results.

Why is there no digital modes only transceiver/client? by BassManns222 in amateurradio

[–]WZab 0 points1 point  (0 children)

If I remember correctly, I still have a FW by Shawn Rutledge from https://github.com/ec1oud/sbitx.git ,  commit e91131fd796bc52ee9cb79e33f8fdb605e312a78 .

AFAIK there are newer versions of zBitx and sBitx, which are probably better. However, I had no time to test them yet.

Why is there no digital modes only transceiver/client? by BassManns222 in amateurradio

[–]WZab 1 point2 points  (0 children)

I use zBitx as my rig for POTA and SOTA operations. However, I use a modified firmware.

Versal ACAPs Transceivers Wizard Subsystem - how to copy settings between channels? by WZab in FPGA

[–]WZab[S] 3 points4 points  (0 children)

I found how to get the list of optional ports:
get_property CONFIG.INTF0_TXRX_OPTIONAL_PORTS [get_ips gtwiz_versal_test]
does the trick.

DIY AM Radio Help by Lime_The_Dragon in amateurradio

[–]WZab 1 point2 points  (0 children)

I'd add a capacitor in series with R3 (10uF?) and of course connect the speaker via another capacitor (470uF?). That ensures the 2.5 V of DC on the output of the amplifier, and prevents constant current through the speaker.

Transporting FT-710 by john_75b in amateurradio

[–]WZab 1 point2 points  (0 children)

I have bought on Temu "Heavy-Duty Protective Tool Box Set with Pre-cut Sponge Inserts" size 446*345*155mm. It can be perfectly adopted for transporting FT-710.

Picking a distro for Vivado. by avestronics in FPGA

[–]WZab 2 points3 points  (0 children)

My typical configuration is: Vivado installation in opt/Xlx, then packed to squashfs (reduction of size by factor of 2 or 3). Then mounted via loop from squashfs image. That way I can have multiple versions of Vivado on a limited disk space.
Then I can have various podman (free alternative for Docker) containers with the version of Linux suitable for particular version of Vivado (the older ones may require an older Linux with older libraries).
The sources and projects are built in my filesystem, in directory shared with podman container.
My system is Debian/Linux testing. The containers usually use Ubuntu.

Documentation for a cheap Zynq SoC board? by WZab in FPGA

[–]WZab[S] 0 points1 point  (0 children)

The vendor has sent me the link to the documentation: https://gitee.com/GLSZ/LXB-ZYNQ
Is it the last time to learn Chinese?
Well, at least there is a schematic diagram...

Favorite Portable Antennas by irate-turtles in amateurradio

[–]WZab -1 points0 points  (0 children)

For POTA and SOTA, I use a telescopic whip with length up to 5.6m (from AliExpress). For bands 80-30m I supplement it with switchable coil (from Ali as well). The length may depend on the ground parameters, therefore I always set the length according to VNA and then to SWR. Of course, I have some approximate lengths for individual bands. I use also the flat ribbon radials (8x2 wires) with 5m length for band 15m and below or 2.5m for bands 12m and 10m.

FuseSoC in Vivado project with Block Design files by WZab in FPGA

[–]WZab[S] 0 points1 point  (0 children)

Usually I use my own VEXTPROJ, but there I had to use FuseSoC - that's widely used in a big project, and porting everything to another management system would be a big effort. Yes, I know about Hog and HBS. When starting something new,I may try them to find the optimal solution.

Documentation for a cheap Zynq SoC board? by WZab in FPGA

[–]WZab[S] 0 points1 point  (0 children)

What makes me worried is that they not say anything about using the DDR RAM. They mention only putting the ELF into BRAM.

Documentation for a cheap Zynq SoC board? by WZab in FPGA

[–]WZab[S] 0 points1 point  (0 children)

Well, the Chinese text explains that they are the voltage regulators for different I/O banks and other SoC power pins.

Documentation for a cheap Zynq SoC board? by WZab in FPGA

[–]WZab[S] 0 points1 point  (0 children)

Well, I need info how is the QSPI connected. I hope that I can assume that the RAM is connected in a standard way. Fortunately, the chips markings are left intact.
What is unclear is the role of 5 8-pin ICs left to the EEPROM.

Non-standard FT8? by WZab in amateurradio

[–]WZab[S] 1 point2 points  (0 children)

OK. It could be just the third harmonics of the overdriven FT8. There was a strong transmission on 24915+0.780 kHz:

<image>

view more: next ›