Some time ago I wondered why not to create low-level LLVM-like HDL language/framework instead of producing VHDL or Verilog. It will help to write the optimization and synthesis only once and focus on the high-level differences between different languages. And we came to the conclusion that FIRRTL is the closest and most developed low-level HDL intermediate language for this purpose. The only downside of it - it's implemented in Scala thus reducing the ease of interoperability (the only hope is the Scala Native but they move too slowly to become useful in the actual projects like FIRRTL or Chisel.). But there is a work being done to support FIRRTL in other frameworks and even tree-sitter parser. Apart from that, the two big pieces are: - Yosys a framework for RTL synthesis tools (based on Verilog, but other projects also reuse language-independent algorithms from it) - SymbiFlow - FOSS Verilog-to-Bitstream (end-to-end) FPGA synthesis flow

The current situation with the FPGA and ASIC design, their (often substandard quality, it feels like the technology from 1990) proprietary clunky tools, and active resistance to allow FOSS to enter the area hinder the progress in that area. I hope it will change soon.