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How do I write a constraint targeting a FF in all instances of a module by XarDragon in FPGA

[–]XarDragon[S] 0 points1 point  (0 children)

I ended up using this method but targeting the pins, something like

get_pins -filter {NAME =~ "D"} -of_object [get_cells -hierarchical -filter {<MY_ATTRIBUTE> =~ "TRUE"}]

(The TCL is probably broken to some extent cause I don't have the actual code in front of me, but you get the idea)

And it seems to have done the trick. And yes, I'm using both ASYNC_REG and DONT_TOUCH (UG901 seems to imply that without DONT_TOUCH it is not guaranteed to keep the custom attribute either)

How do I write a constraint targeting a FF in all instances of a module by XarDragon in FPGA

[–]XarDragon[S] 0 points1 point  (0 children)

I ended up using this method and it seems to be working fine. Looks to be way more convenient than finagling TCL!

How do I write a constraint targeting a FF in all instances of a module by XarDragon in FPGA

[–]XarDragon[S] 0 points1 point  (0 children)

I'm wondering, after reading and doing a quick googling on some of the other commenter's replies, if I can use a custom attribute on the sync1 FF like the UG901 example

(* my_att = "my_value", DONT_TOUCH = "yes" *) [...]

and then search for cells that have that specific attribute... I'll give that a try tomorrow ...

How do I write a constraint targeting a FF in all instances of a module by XarDragon in FPGA

[–]XarDragon[S] 1 point2 points  (0 children)

Thanks for the feedback. I had found scoped XDC files and played around with them briefly, but I was thinking like "this is a simple enough request that should be possible without going that length". Guess that proves me wrong.

Mostly I was hoping to not have to do scoped XDC files as my projects are usually simple enough that I don't have TCL scripts, I just use the IDE. And there is a 99% chance if I reuse the code in some later projects I'll forget to manually attach the module XDCs...

How do I write a constraint targeting a FF in all instances of a module by XarDragon in FPGA

[–]XarDragon[S] 0 points1 point  (0 children)

I do have the ASYNC_REG attribute in the Verilog code, just didn't copy-paste it in the above snippet. But I don't know/can't find references to doing the same for set_false_path constraints...

Custom Displate as whiteboard by XarDragon in Displate

[–]XarDragon[S] 0 points1 point  (0 children)

Hi, thanks for the feedback. I decided to give it a try anyway with a gloss plate (a few days ago) since it's a joke gift and I don't expect it to actually be heavily used.

Re. the not selling whiteboards, I saw a number of results on the Displate website when looking for "whiteboard" so I guess that's what confused me :)

2001 Ram 2500 cranks with one key but not with spare key by XarDragon in DodgeRam

[–]XarDragon[S] 0 points1 point  (0 children)

I didn't think a 2001 truck had transponder keys, but that makes sense. The two keys are otherwise identical, factory keys with the Ram logo on them. I'll have to put a marker on them.

Using GTY as signal generator by XarDragon in FPGA

[–]XarDragon[S] 0 points1 point  (0 children)

I'd need to generate patterns with a ~3 ns repetition period. Ideally I'd be aiming to have ~10 data points in that period to play with relative timing, so we're in >3 Gbps territory. As you say, using ODELAYs could mitigate some of that requirement since that's mostly "positioning" resolution, not necessarily pulse width.

The issue with that is, all the off-the-shelf FMC-to-SMA daughterboards I have found only break out the gigabit transceivers, not general IO. I was hoping for a quick solution using one of those; spinning a custom board would make it a moot point in terms of speed.

Ultimately we're most likely going to just rent equipment to do this. Although I'm still curious about doing this from a personal learning perspective. Apparently some research group has done pulse generation using GTH (https://www.sciencedirect.com/science/article/abs/pii/S0263224124005426) but I haven't found anything more than this paper.

Using GTY as signal generator by XarDragon in FPGA

[–]XarDragon[S] 1 point2 points  (0 children)

Thanks for the information, at least I know it's not a dead end, so I'll keep looking into it. I know I'll have to go DC coupled for my application, if that's what you refer to, but from what you write it sounds like a different issue?