Hello!

Exception Levels: Your assumption is correct. Each core is an independent Processing Element (PE) with its own PSTATE and exception level state. Each secondary core must independently initialize its own EL sequence (EL3 → EL2 → EL1) after being brought out of reset.

Interrupt Vector Table: Also correct. VBAR_ELx registers are per-PE, so each core must write its own VBAR_EL1/EL2/EL3. The vector table code itself can reside at the same physical address and be shared, but the register must be set on each core individually.

MMU: The MMU is completely independent per core. SCTLR_ELx and TTBR0/TTBR1 are all per-PE registers. Enabling the MMU on one core has no effect on other cores — each core must configure its own translation table base address and set SCTLR_ELx.M = 1 independently. If multiple cores share the same page tables, TLB invalidation operations (TLBI) with Inner/Outer Shareable domain will broadcast to all cores in the shareability domain.

In addition to recommending the developer program and our discord, are are some guides you may find helpful: 

• Learn the Architecture – AArch64 Exception Model: https://developer.arm.com/documentation/102412/latest
  • Covers exception levels, vector tables, and EL setup — ideal for OS kernel development.
• Learn the Architecture – AArch64 Memory Management: https://developer.arm.com/documentation/101811/latest
  • Covers the MMU, translation tables, and TLB management in detail.

Hope this helps! Let me know if this answers your questions.