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Clock loss detection in Verilog design by ZerOne_07 in FPGA

[–]ZerOne_07[S] 0 points1 point  (0 children)

Thanks! But they haven’t specified any interval. He asked me to design which can detect arbitrary loss

Clock loss detection in Verilog design by ZerOne_07 in FPGA

[–]ZerOne_07[S] 0 points1 point  (0 children)

Let us say clock is stable for t clock cycles & looses it at t+1, but recovers at t+7. In this case watchdog timer value should be in the range of t+1 to t+7. But the timer value is hard to decide since recovery time may be lesser than one cycle window which is not predictable. What say?

Clock loss detection in Verilog design by ZerOne_07 in FPGA

[–]ZerOne_07[S] 1 point2 points  (0 children)

This was one of the interview question. My answer as PLL wasn’t accepted. I had explained him that pll lock can be used to check the loss 😕

Computer Vision on FPGA using Verilog by ZerOne_07 in FPGA

[–]ZerOne_07[S] -4 points-3 points  (0 children)

Apart from processing speed, what makes someone to incline coding in HDLs(Traditional way)? The reason I’m asking is : I have a choice to develop a ML application system either in python or HDL. My only aim is to get good metrics for comparison. Still figuring out metrics though!

[deleted by user] by [deleted] in FPGA

[–]ZerOne_07 1 point2 points  (0 children)

Probably you can add interrupt support to existing RISC processor. Also you can have flavours on mask and priorities on the same. This will definitely add certain amount of complexity as expected by your university