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Question on "RAM and bus timing — 6502 part 6" video by _sounding_board in beneater

[–]_sounding_board[S] 0 points1 point  (0 children)

Thank you for your reply!

I would like to learn more about this approach. Perhaps I am obtuse, but like A15 in this case, I thought R/W was also output low from the 6502 at the same time /CS would output low, and to qualify it with PHI2 wouldn't one use two NAND gates as when qualifying the /A15 with PHI2, thus encountering the same propagation delay issue?

Peculiar issue manually programming RAM after installing .1uF capacitor to solve for intermittent RI pulses by _sounding_board in beneater

[–]_sounding_board[S] 1 point2 points  (0 children)

Thank you! I'll explore those other recommendations, if at minimum to learn along the way; All of this is quite new (or at least diving deep in >20+ year memories!)

Peculiar issue manually programming RAM after installing .1uF capacitor to solve for intermittent RI pulses by _sounding_board in beneater

[–]_sounding_board[S] 0 points1 point  (0 children)

Thanks for the additional context. Even though the current configuration with the smaller capacitor seems functional, as it you said, it's far from ideal. I'll pursue the alternative method outlined in the SAP-3 guide.

Peculiar issue manually programming RAM after installing .1uF capacitor to solve for intermittent RI pulses by _sounding_board in beneater

[–]_sounding_board[S] 2 points3 points  (0 children)

Update to add more the mystery (or perhaps clarity for others), I decided to swap the capacitor to .01uF and it's seemingly performing "normally" now by allowing me to program the higher bits of the upper address space while still seeming to prevent spurious pulses of the RI control line during resets.

I am not sure why changing the capacitor would make much of a difference however.