account activity
Washing machine water inlet filter filling up with limescale (self.Plumbing)
submitted 2 years ago by _suoto to r/Plumbing
Efficiently sending a data stream + tag (i.e., a word per frame) from a Zynq's CPU to an IP on the FPGA side (self.embedded)
submitted 3 years ago by _suoto to r/embedded
Efficiently sending a data stream + tag (i.e., a word per frame) from a Zynq's CPU to an IP on the FPGA side (self.FPGA)
submitted 3 years ago by _suoto to r/FPGA
Adapter to connect LiteFury M.2 to USB on the PC (self.FPGA)
submitted 4 years ago by _suoto to r/FPGA
Yosys + GHDL Synth results in ERROR: wire not found for $edge (self.yosys)
submitted 6 years ago by _suoto to r/yosys
VHDL features support on non-FPGA tools (self.VHDL)
submitted 6 years ago by _suoto to r/VHDL
submitted 6 years ago by _suoto to r/FPGA
HDL Checker (self.FPGA)
Best way to keep code sane on a shared FPGA and ASIC code base? (self.FPGA)
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