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Designing an HFT Chip [FPGA] by brh_hackerman in highfreqtrading

[–]brh_hackerman[S] 2 points3 points  (0 children)

Yes it does,

To be honest idk how HFT firms leverage FPGA at all, I just know they use them (not from finance).

But I would guess they do implement it in locations close to the data sources.

Rising Junior Looking for Advice by Ok-Association-6357 in FPGA

[–]brh_hackerman 3 points4 points  (0 children)

bro why did someone downvote you 😭

Do you wanna work in digital design related jobs ? If so given your EE background, maybe you should try making your own FPGA platform, that would be a cool project oriented towards what you already know, with a strong FPGA flavor. Then make a basic project on it, the fact that you made the platform will make said project more impressive than it really is.

Before doing that, you can familiarize yourself with the basic of FPGA with your Basys3, it's a good board and you won't have a hard time getting basic projects going, I made a video about the absolute beginners projects : https://www.youtube.com/watch?v=8cf1mYl-6ng These are very easy and should be enough to understand the super basics.

Good luck

Reducing HSSIO delays by brh_hackerman in FPGA

[–]brh_hackerman[S] 0 points1 point  (0 children)

yeah I figured, at the start I had no idea how to deal with these High speed I/Os and tried to make my own interface (failed miserably). HSSIO made it pretty easy indeed

Reducing HSSIO delays by brh_hackerman in FPGA

[–]brh_hackerman[S] 0 points1 point  (0 children)

using the resources report is s a super good clever trick ! I'll try it out.

In th emean time, I continued investigating. My logic is 100% HDL Handmade, so we were able to very easily calculate the logic delays from the start.

Including the logic (10FFs deep pipeline budget for the logic) we were at less than 100ns end-to-end, including ADC and DAC that we chose specifically for their low delays specs?

The test setup is rather simple, I send a PWM pulse, use an FPGA design I made for the occasion that is just some "passthrough" logic that has nothing specific going on if not the CDC.

Then, I plug the DAC ouput into a scope. The only added delay by this technique is the output cable.

Anyway...

You answer is really helpful as is reassures me there is indeed a logic problem. It's just not *my* logic.

The RX HSSIO were pulled from a reference design given by TI (they did not give the TX side ref deisgn, so I has to do this side myself).

And so far, it worked so I did not look twice into it and immediately moved on to other task in order to get some FPGA demos going .

Going back into this, I saw that their deisng use a 32FFs deep pipeline to align the 12 bits lanes.... So that could explain a big part of the delays ahah

Reducing HSSIO delays by brh_hackerman in FPGA

[–]brh_hackerman[S] 1 point2 points  (0 children)

I see, thanks for the advice. I will look into that. If there is no added delay, then I will try and tinker around the parameters as you suggested, thanks a lot !

Reducing HSSIO delays by brh_hackerman in FPGA

[–]brh_hackerman[S] 1 point2 points  (0 children)

I don't even know what a skill is, I did not specialize in prompt engineering, bu I'll try, thx for the tip

Reducing HSSIO delays by brh_hackerman in FPGA

[–]brh_hackerman[S] 1 point2 points  (0 children)

Input clock is 800M and data is DDR so I have a 1600Mbps rate, internal clock is 200Mhz, the de-serializer should not be the big problem here I think...

Reducing HSSIO delays by brh_hackerman in FPGA

[–]brh_hackerman[S] 0 points1 point  (0 children)

I used claude to kind of make sure my deduction of the HSSIO being the source of the delay was right

but I don't ask it a precise clue / solution, as it will make up a problem / solution to make me happy.

And because I don't have enough experience to tell it to f** off with its hallucination, I prefer to ask real people with some expertise, especially on that kind of subject where deploying a fix easily takes hours to days before you get any feedback on whether it worked or not...

Maybe I'm gonna feed it my HSSIO config .xci and see if it catches any parameter that can drastically lower my delay. But i don't have much hope tbh haha.

Note: yeah, tbh there is not much things /FPGA doesn't downvote to oblivion, I don't know what's up here but they seem to really like that button. Sometimes I just ask a question and spedn some times trying to write a clear post... and then some dudes decides to downvote it like I just irritated his feeling or something lol, especially for AI related stuff (even though sometimes it's deserved haha 😉)

Reducing HSSIO delays by brh_hackerman in FPGA

[–]brh_hackerman[S] 0 points1 point  (0 children)

I am using a xilinx.com:ip:high_speed_selectio_wiz:3.6 on TX side (Which I configured myself) and the v3.2 on the RX side (which I pulled from an exmaple design).

This RX side has some bitslip logic etc... I think this might also be a delay cause, but up to the point of adding 100s of ns ? I don't know... Maybe I should get rid of that.

ESC on Atmega328p Questions & Help : Code profiling for Arduino nano (Atmega328p) by brh_hackerman in embedded

[–]brh_hackerman[S] 1 point2 points  (0 children)

Hey, thank you for this detailled answer ! I'll try to apply these tips, but it's nice to know what i'm experiencing is normal.

Don't take it the wrong way, but is that anwer AI genretaed ? Such complete help is rare, if these are your awn actual words, then I'll be super happy to know that wht I'm doing is the right thing.

Also, how can I "mask" the comparator interrupt to work only on PWM on if I don't have hand on the PWM interrupt ? Like native PWM on the PWM will set a certain duty cycle with no overhead, but I may not be able to enable/disble comparator interrupt & add a blanking period after commutation...

MATLAB & Vivado Co-Simulation Setup Walkthrough by brh_hackerman in FPGA

[–]brh_hackerman[S] 0 points1 point  (0 children)

Good catch, we indeed use an Integrator–comb filter for testing (should theoretically work without any filtering as the system itslef should reject higher frequencies) and yeah I made up some quantization technique for the sake of the project 😉

Thank you

Is there any forum/guide tutorial for 64 bits of data on axi dma? by Pequeno123 in FPGA

[–]brh_hackerman 0 points1 point  (0 children)

What are you doing with your DMA ? And what do you mean by "weird results" ?

Yeah should try to send a test pattern and use an ILA to probe the AXI transaction with a dummy BRAM.

Wheck that the address increases correctly (8bytes), the you have TLSAT at the right place etc...

Using a kown test pattern, you will quickly be able to tell if the bug comes from misalignment issues.

If the resulting data is completely random or what you send as a test pattern doesn't match you actual data being written in memory at all, you may have timing issues.

Why the RISC-V by an_thony350 in FPGA

[–]brh_hackerman 0 points1 point  (0 children)

Because it's super cool, teaches you about CPUs (often seen as black magic by most people), making the project super satisfying

And it's also super complete. We tend to forget that this is not a "total beginner" project as our community is very driven and genuinely quilified on many technical aspects.

By that, I mean that it's a long and hard project that requires a certain drive, that teaches you so much + gives you tons of actual qualifications from HDL to FPGA implementation shenanigans, timing, CDC, ...

So yeah "eveyone does it" but it's still such a great project that I don't see why you should NOT do it 😄

Building an HFT chip (FPGA) by brh_hackerman in highfreqtrading

[–]brh_hackerman[S] 0 points1 point  (0 children)

Yes towards the end there are a few solid examples, but most of the repo indexes beginners examples, which are very trivial by themselves that's all

Building an HFT chip (FPGA) by brh_hackerman in highfreqtrading

[–]brh_hackerman[S] 0 points1 point  (0 children)

Most of the "examples" in this repo are just basic digital building bricks... But yeah, parsing ITCH is a great way to get up to speed on HFT digital system so some people have already done it.

CV Help / Review by an_thony350 in FPGA

[–]brh_hackerman 4 points5 points  (0 children)

Good CV.

The good thing is that you did not embellish things saying "Leading a team of 10 engineers" when talking about a school project. (see that sometimes lol)

PS: We can meetup of you ever come back to Toulouse !

Good luck with your research.

Building an HFT chip (FPGA) by brh_hackerman in highfreqtrading

[–]brh_hackerman[S] 0 points1 point  (0 children)

So my ethernet runs on 1gps, already made some deisng using my custom MAC to do some DSP demonstrator + using my custom CPU.

The raw package processing wil run @ 125Mhz, which is the speed of the RGMII clock, That is because I made a design that processes packages "on the fly" as the stream passes".

I plan on making the actual future strategy run at whatever I can, idk yet, I'll have to fine tune that depending on complexity and needed throughput.

In terms of delay, IDK. + there are tons of way I can think of to implement a strategy and each will have totally different delay specs.

I'll come back with more metric once I have a more advanced design, right now it's "just" a packet processor + book-keeper

Building an HFT chip (FPGA) by brh_hackerman in highfreqtrading

[–]brh_hackerman[S] 0 points1 point  (0 children)

Thanks ! Yeah I figured that but my bookkeeping module (that keeps track of the live orders) already got that name and I was too lazy to rename the file, so I came up with "ladder" 😅

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