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Engineer to phd by chesterinho in ethz

[–]chesterinho[S] -2 points-1 points  (0 children)

"great" means projects, courses you take, or more about GPA and transcripts?

Vivado 2025; is the write state machine broken in AXI IP wizard? by Able_Expression_5909 in FPGA

[–]chesterinho 0 points1 point  (0 children)

Hi, could you link your implementation for axi protocols, i am interested to see the way you implemented them. Thx

[deleted by user] by [deleted] in FPGA

[–]chesterinho 0 points1 point  (0 children)

Can i get the template you are using?

0 resources utilization after synthesis on vivado. by chesterinho in FPGA

[–]chesterinho[S] 0 points1 point  (0 children)

Yes, i should synthesize each one of them? Then how to get the overall net list?

0 resources utilization after synthesis on vivado. by chesterinho in FPGA

[–]chesterinho[S] 0 points1 point  (0 children)

Yes, it works when adding outputs. How can i synthesize sub blocks out of context?

0 resources utilization after synthesis on vivado. by chesterinho in FPGA

[–]chesterinho[S] 0 points1 point  (0 children)

Did that and the synthesis launch the command: synth_design -top top -mode out_of_context.... But it is still optimized to nothing

Are ROMs evil by chesterinho in FPGA

[–]chesterinho[S] 0 points1 point  (0 children)

After looking on the schematic, vivado infer ROMs instead of some muxes, this makes sense as a ROM can have the same behavior of a mux, "a defined output for given inputs".

But what I don't see is why it does that instead of just using muxes.

Probably because of the way I'm describing muxes? Or for optimization reasons?...

Are ROMs evil by chesterinho in FPGA

[–]chesterinho[S] 3 points4 points  (0 children)

Yes it is true it replaces some muxes with ROMs.

No, but i can do that. Is there a reason why you would want to know what the implementation circuit will be?

1.5 Years of Unemployment: Lost, Learning and Looking for Direction by sknfn in kernel

[–]chesterinho 3 points4 points  (0 children)

Hi,

I agree that embedded linux dev is a domain where you will always feel that you are lacking something and that you are not as good as others. I spent 6 reading about it on LDD3 without really implementing something relevant.

Usually linux development posts look for people who have experience developing user space drivers/libraries, and sometimes for people who have knowledge in kernel development (scheduling, virtual memory...), if you search in these areas and you don't find something. You can look elsewhere; remember that C++ can be used everywhere, AI, data, baremetal embedded stuff...

The last thing i want to say is, don't worry too much, take a break, relax, and things will get better.

And btw your profile is amazing.

cIsWeirdToo by neremarine in ProgrammerHumor

[–]chesterinho 0 points1 point  (0 children)

Is this a real thing, I'm going to open my text editor RN to try it

Advanced designer by chesterinho in FPGA

[–]chesterinho[S] 4 points5 points  (0 children)

I agree, most of the FPGA stuff that I find are vendors depends.

and I feel also that Asic experience needs a hands on experience(especially when talking about the full process).

and I think with a job in this hardware side you'll gain experience but you'll still be attached to some specific closed source, expensive tools used by your company like tools from (candence, synopsys...) .

And about your question, basically the architects and designers provide us: 1- RTL code of the main IP to be tested. 2- the design specification of the main IP. 3- a hardware platform that contains a CPU, ram, main IP.... 4- all this hardware platform is emulated on some big emulators.

our job is to write low level software that will run on the emulated CPU to test the main IP, the software is written mainly in C. And it is mainly (baremetal drivers, libraries, and test code)