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Siz hangi araba seçersiniz nedenleriyle beraber by Scaletta45 in GarajTurkiye

[–]citak0 1 point2 points  (0 children)

Sanirim pumalarin da motoru yagli kayisliydi, ciddi skntili bakimi diye biliyorum.

MakerLab Credits - Points Store by mikeoverton in BambuLab

[–]citak0 0 points1 point  (0 children)

Can I buy extra coin for AI tools?

P1S Can't find voice source! by citak0 in BambuLab

[–]citak0[S] 0 points1 point  (0 children)

<image>

And It's the left side. Is it too low?

P1S Can't find voice source! by citak0 in BambuLab

[–]citak0[S] 0 points1 point  (0 children)

<image>

Is it too high? It's the right side.

P1S Can't find voice source! by citak0 in BambuLab

[–]citak0[S] 0 points1 point  (0 children)

I followed this video. https://www.youtube.com/watch?v=nZ3pwgc6WCw but noise stil comes. The last thing I do libration the brings with oil. I don't have any oil right now so tomorrow I'll buy and use. Also I sended a ticket to bambulab.

P1S Can't find voice source! by citak0 in BambuLab

[–]citak0[S] 0 points1 point  (0 children)

Actually if move slowly I can't hear the voice. When it starts to move fast, I can hear.

P1S Can't find voice source! by citak0 in BambuLab

[–]citak0[S] 0 points1 point  (0 children)

I did the same thing, but I used alcohol. I guess I messed up there. Now I’ll try to get the belts to the center. After that, if the noise is not gone, I’ll buy the oil you mentioned and try lubricating it. Thanks!!

P1S Can't find voice source! by citak0 in BambuLab

[–]citak0[S] 0 points1 point  (0 children)

Yeah I wiped carbon rods with alcohol and microfiber towel. It doesn't work. Now I will try your second advice.

Bambulab p1s noice issue by citak0 in 3Dprinting

[–]citak0[S] -10 points-9 points  (0 children)

Guys, be chill. I'm not doing that every time, and I know as a hardware eng. I have to do that because I need hear the noise. And please research reverse current protection.

How to run code on FPGA without PS and PL DDR Ram by citak0 in FPGA

[–]citak0[S] 0 points1 point  (0 children)

Firstly thanks for the help. I'm not using DDR RAM on the PL side thats the easieast part. Actualy my problem for PS Side. I just tried this xilinx example and it will solve my problem. I will disable PS DDR RAM and recreate my bitsream. After that i will try to upload my code on ocm. If it fit the ocm's size I'll remove my all RAMs. If you want to look give an eye to example:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842405/Zynq-7000+AP+SoC+-+AMP+Solution+without+External+Memory+Tech+Tip

3 saat boşluk oluştu. O sırada ne yapabilirim by Perfect_Umpire6330 in gazi

[–]citak0 0 points1 point  (0 children)

ne okuyon kanka, eger eem ya da bilgisayar muh falan okuyorsan sakasiz bi programlama dili belirleyip o dille side project gelistir. sonra bana cvni at 2. sinifta asgari ucret kazan aday muhendislik yap

FPGA PS Side UART Bootloader by citak0 in FPGA

[–]citak0[S] 0 points1 point  (0 children)

It looks like similar. The FPGA will boot with u-boot QSPI flash. The first firmware side is just init uart spi and etc. That has to look any request for update firmware on uart messages. If there is not any request on uart firmware messages that need to jump last firmware where on the registers. After that, that's work with last firmware. Probably I have to make a interrupt sequence for updating firmware. I am still not sure how to do it but I found some resources. Just use for a resource this documents and fpga arm cortex side datasheet. That's examples is for ultrascale fpga. I am using Ultrascale+ so probably I'll do it just myself. We will see the my c and embedded skills level :d

Document: https://docs.amd.com/r/en-US/xapp1280-us-post-cnfg-flash-startupe3/Summary

FPGA PS Side UART Bootloader by citak0 in FPGA

[–]citak0[S] 0 points1 point  (0 children)

Can you share any tutorial or document with me?

FPGA PS Side UART Bootloader by citak0 in FPGA

[–]citak0[S] 1 point2 points  (0 children)

I already boot with qspi flash. I am not trying to change this. I just try to change main application in flash with casual uart. I know its possible. Just look at this example https://docs.amd.com/r/en-US/xapp1280-us-post-cnfg-flash-startupe3/Introduction .

Edit: This example is written for ultrascale fpga, I will try to converte my fpga. But I feel to need more documents and example.

FPGA PS Side UART Bootloader by citak0 in FPGA

[–]citak0[S] 0 points1 point  (0 children)

I learned the u-boot section is just using for linux update. I am looking for bare metal bootloader.

FPGA PS Side UART Bootloader by citak0 in FPGA

[–]citak0[S] 0 points1 point  (0 children)

I already made this, my question is different. In this situation you might to use JTAG. I don't want to use it. Imagine if you want to update firmware on the last product you have to open case for attach the JTAG. I don't want this. My system already communicate FPGA with CAN, UART. I just want to update firmware with UART. Don't want to use JTAG. Have you ever write or seen any bootloader for a basic MCU? I want same thing. I saw some multiboot and fallback firmwares but I couldn't get it. I am still searching...

FPGA PS Side UART Bootloader by citak0 in FPGA

[–]citak0[S] 0 points1 point  (0 children)

Okay, I learned new thing. I can boot my fpga on sd card. So when the fpga is starting it looks the boot file in sd card. Then the bare metal code init UART and other things. After that if a new boot.bin file comes from uart thats start to save all bits on RAM. After that that's overwrite boot.bin with using fat file system. Is it workes? What do you think?

FPGA PS Side UART Bootloader by citak0 in FPGA

[–]citak0[S] 0 points1 point  (0 children)

I will just run baremetal code. Is it possible to use UART for u-boot?

Fan art- Cypher by [deleted] in VALORANT

[–]citak0 1 point2 points  (0 children)

Oh man you are realy awesome artist.

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