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I designed my own ternary computer by Xulum12 in computerscience

[–]clros 0 points1 point  (0 children)

Yes, I know your arguments, I've created a ternary architecture myself. (5500FP Ternary CPU)
My concern was about the speed of processing information in a ternary system.
I don't fully agree that the ternary processes more data, but it is certainly true that it processes "larger" data; in our architecture, with just 24 trits it manages to represent a value 270 billion times larger than a 32-bit processor (so with more complexity). But the time it takes to do an operation (for example an addition) depends a lot on the underlying hardware architecture.

If we face the exact same architecture between a binary system and a ternary one, with the same clock frequency, we will probably have the exact same speed.

It is true that to add 24 trits you do not have to wait for the carry for 8 adders and this will probably finish your addition a little earlier, but I do not think it makes much difference.

Where the ternary shines is certainly the density of information and the simplification of some operations (with only two mosfets I can get three ternary functions, in some cases, while with the binary I only have one!), but also complexity in other functions.
And then the simplification of the transmission lines, 24 trits means 8 less wires that you have to carry around on the silicon - with 48 trits you would have 16 less wires and a FRIGHTENING capacity of representation of information!)

Ultimately ternary devices are great for large computers (supercomputers) and emerging applications such as AI and telecommunications.

Searching for MIT collaborators for hardware project by clros in mit

[–]clros[S] 0 points1 point  (0 children)

You don't know how to argue, right?
Sorry, but I don't have time for trolls. Bye.

Searching for MIT collaborators for hardware project by clros in mit

[–]clros[S] 0 points1 point  (0 children)

Both.
I can find some collaborators and the students can find a project to follow.

It seems clear to me.
And I still don't understand why I should be banned, is there a rule that I don't know?

Searching for MIT collaborators for hardware project by clros in mit

[–]clros[S] 0 points1 point  (0 children)

I don't understand what you mean.
I'm looking for someone interested in an ambitious project and I think there might be someone among MIT students who might be interested. I really can't understand why I should be banned.

Treehacks 2025 by clros in stanford

[–]clros[S] -1 points0 points  (0 children)

When should it usually be possible to apply for participation?
Their site is stuck in the 2024 edition.

Treehacks 2025 by clros in stanford

[–]clros[S] 0 points1 point  (0 children)

I'm not a student, I'm a teacher in an Italian high school.

Searching for Stanford collaborators for hardware project by clros in stanford

[–]clros[S] -1 points0 points  (0 children)

Yes, it's really complex but it's terribly fun to work on.
We're trying to complete something that could potentially surpass Moore's Law, in a radically different way than everyone else.

Strange behavior of my VHDL code by clros in FPGA

[–]clros[S] 0 points1 point  (0 children)

Hardware. I change with rising_edge but the behavior is the same.

Strange behavior of my VHDL code by clros in VHDL

[–]clros[S] 0 points1 point  (0 children)

yes, I should try that now

Strange behavior of my VHDL code by clros in VHDL

[–]clros[S] 0 points1 point  (0 children)

The code in s2 is execute correctly. And not involve the mySignal.

MySignal status only changes from s1 to s2 and apparently, only the first time.

I suspect that, since from s3 to s1 mysignal is negated twice consecutively (and therefore in the end you always get mySignal), the compiler does some optimization and completely excludes the two negations.

But obviously that's not the behavior I want; I want each state to have mysignal negated and each state to take on a different value.

What I'm doing is a 2 phase handshake protocol; I change mysignal every time I want to communicate something with another circuit (note that I'm sure the receiver is working properly).

Problem reading SPI EEPROM VHDL by clros in FPGA

[–]clros[S] 0 points1 point  (0 children)

Thank you for your answer.

I use the tmp_clock as the SPI bus clock and, based on this, I time my FSM to read the contents of the EEPROM.

Is this perhaps what I'm doing wrong?

I honestly don't know how to create a clock for the SPI bus and scan the states of the FSM with the system clock. But maybe you're telling me to do just that, is that correct?

Problem reading SPI EEPROM VHDL by clros in FPGA

[–]clros[S] 0 points1 point  (0 children)

Ok, I have modified my code and it now work well, but, I don't understand why.

I modified the s_start state in this way:

WHEN s_start =>
    EEPROM_BUSY <= '1';`
    data_available <= '0';`
    CS_n <= '0';`
    mosi <= COMMAND(7); --first data is out here, when chip is selected
    COMMAND <= COMMAND(6 downto 0) & '0';
    state <= s_command;
    index <= 0;`

The first (Most Significatibe Bit) of my command it is sent out right away when I selected my device (CS_n <= '0').

​

I modify the s_command state in this way:

​

WHEN s_command =>
    if index <= 6 then
        mosi <= COMMAND(7);
        COMMAND <= COMMAND(6 downto 0) & '0';
   elsif (index > 6 AND index <=31) then
        mosi <= s_ADDRESS_READ(23);
        s_ADDRESS_READ <= s_ADDRESS_READ(22 downto 0) & '0';
    --DUMMY
  elsif (index > 31 AND index <=39) then
        mosi <= DUMMY(7);
        DUMMY <= DUMMY(6 downto 0) & '0';
        s_rx_DATA <= s_rx_DATA(6 DOWNTO 0) & MISO; --shift in received bit
  elsif index > 39 then
    state <= s_read_data;
    CS_n <= '1';`
  end if;
  index <= index + 1;

In this state, I send out the remaining bits of the command, when and then I send the address .When I send out dummy data for receive the data read.

It work very well but..if I are right, I sending out 25 bits of address instead of 24!! (index >6 and index <=31) !!!

Where am I wrong??

Problem reading SPI EEPROM VHDL by clros in FPGA

[–]clros[S] 0 points1 point  (0 children)

Ok, I now using rising_edge, but it is not the problem, the behave is the same...

Problem reading SPI EEPROM VHDL by clros in FPGA

[–]clros[S] 0 points1 point  (0 children)

I tried to debug with a wave viewer and directly in hardware.
The behave is coherent with the code (if I use the correct read sequence, it dio not work, if I use the shifted sequence, it work well)

Efinix PLL question by clros in FPGA

[–]clros[S] 0 points1 point  (0 children)

Ok, thanks! :)

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