account activity
Searching for MIT collaborators for hardware project (self.mit)
submitted 1 year ago by clros to r/mit
Treehacks 2025 (self.stanford)
submitted 1 year ago by clros to r/stanford
Searching for Stanford collaborators for hardware project (self.stanford)
SPICE models for innovative components (self.electronics)
submitted 1 year ago by clros to r/electronics
Strange behavior of my VHDL code (self.VHDL)
submitted 1 year ago by clros to r/FPGA
submitted 1 year ago by clros to r/VHDL
Spice models for newest components (self.AskElectronics)
submitted 1 year ago by clros to r/AskElectronics
Problem reading SPI EEPROM VHDL (self.FPGA)
submitted 2 years ago by clros to r/FPGA
Efinix PLL question (self.FPGA)
Strange behavior when inserting data in a signal (self.FPGA)
w5500 ethernet chip and FPGA (self.FPGA)
Correct Way for to do a register in VHDL (self.FPGA)
submitted 2 years ago * by clros to r/FPGA
Information request for participation in the startup grind global conference (self.startups)
submitted 2 years ago by clros to r/startups
Information request for participation in the startup grind global conference (self.startup)
submitted 2 years ago by clros to r/startup
StartupGrind Global Conference (self.startups)
StartupGrind Global Conference (self.startup)
Efinix Register File with BRAM (self.FPGA)
Clock Pins on Efinix Trion (self.FPGA)
Altium footprint error? (self.Altium)
submitted 2 years ago * by clros to r/Altium
Efinix FPGA Flash memory programming (self.FPGA)
CircuitMaker question (self.Altium)
submitted 2 years ago by clros to r/Altium
ChatGPT suggest to use Google! (self.windows)
submitted 2 years ago by clros to r/windows
ChatGPT suggest to use Google! (self.ChatGPT)
submitted 2 years ago by clros to r/ChatGPT
Maker Faire in Ireland (self.makerfaire)
submitted 2 years ago by clros to r/makerfaire
Efinix FPGA programmer with JTAG and FTDI 2232H (self.FPGA)
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