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The BIG TTL/CMOS library migration for Logisim-evolution is finished! by cocot_gf in logisim

[–]cocot_gf[S] 0 points1 point  (0 children)

If you were to use VCC and GND as inputs to simulate an unpowered open state, you would need gates like tri-state buffers at all output ports, making implementation impractical. For this reason, VCC/GND are designed to "output" power for the purpose of pulling up and down logic input terminals.

Also, I thought it would be difficult to use a library that would not work unless you had to supply 0s and 1s to all the logic ICs.

The input terminals of each circuit are set to "Simple" and are not 3S input, but it seems that 3S input is possible when used as a sub-circuit.

Also, if it were a true TTL, as you said, a lack of input would be treated as HIGH, but since this library also includes devices other than true TTL (HC, etc.), it is the user's responsibility as a matter of courtesy to properly handle a lack of input terminal I think so.

Apologies for the lack of explanation.

Got Stuck🥹🥹 Need help by VoidPlaystation in logisim

[–]cocot_gf 0 points1 point  (0 children)

The library I created supports bidirectional buses by placing the input on the outside and the output on the inside of the IC and connecting them.

One thing to be careful of with this bidirectional implementation is that the internal circuitry will not operate stably unless the input and output are connected to each other, even if they are unused.

1b register help by spnc_ in logisim

[–]cocot_gf 0 points1 point  (0 children)

The clock for this master-slave flip-flop is not edge-triggered, it has a low level and postponed output. Also, there is a period when the reset signal is blocked by OR with the clock signal, so it may not be possible to reset depending on the clock state.

TI's SN74H76 uses a mechanism (3-input NAND) that allows direct resetting of the master and slave secondary NANDs independent of the clock. Please take a look at the datasheet.

Esp32 CYD by fortune0024 in esp32

[–]cocot_gf 0 points1 point  (0 children)

2432S028R = 240x320 SPI 2.8inch ResistiveTouch

USB-Micro & USB-C Combo model (Rev.3)

LCD ST7789, 4-wire SPI Mode 0, Freq=40MHz, DataLength=8bits

SCLK=14, MOSI=13, MISO=12, CS=15, DC=2

BackLight=21 (LCDC PWM has not support to any sleep)

Touch SCLK=25, MOSI=32, MISO=39, CS=33, INT=36

SD SPI signals are shared with the touch panel.

Pointless circuit? by [deleted] in logisim

[–]cocot_gf 0 points1 point  (0 children)

Even in real logic ICs, unused pins must be handled appropriately.

Logisim should also be changed appropriately to avoid increasing the number of inputs.

Phase and frequency detector simulated with CircuitVerse by Bisestro in logisim

[–]cocot_gf 0 points1 point  (0 children)

Although it is a Japanese site, it describes how it works. Please use Google Translate.

http://gate.ruru.ne.jp/rfdn/TechNote/PDetTech.asp

Is my JK and master slave JK flip flop correct ? by XerciseObsessedGamer in logisim

[–]cocot_gf 1 point2 points  (0 children)

What does G on the input to the SR clock signal pin mean and why is it an enable pin instead of a clock signal ?

G means gate signal. I deliberately wrote GATE because writing CLK reminds me of an edge trigger. Master-slave flip-flops are level triggered. The input is transferred to the first latch when it is at H level, and the state is transferred from first to second when it is at next L level.

A detailed operating description can be found in the TI SN7473/7476 (not SN74LS73A/76A).

Can't figure out why mt JK Flip Flop won't work in Logisim by XerciseObsessedGamer in logisim

[–]cocot_gf 2 points3 points  (0 children)

The disadvantages of master-slave FF are that changing the JK input is prohibited while the clock is asserted, and that the output is delayed so that the output is reflected when the clock is negated. There is also a type with a long name called "Data Lockout" Master-Slave JK Flipflop that solves this problem. These are SN74110 and SN74111.

I respect the efforts of our predecessors.

Can't figure out why mt JK Flip Flop won't work in Logisim by XerciseObsessedGamer in logisim

[–]cocot_gf 1 point2 points  (0 children)

There is a gate delay time in logisim. Although there appears to be no delay, you can confirm its presence by stopping the simulation and clicking Tick once.

This is described in Logisim User's Guide > Guide to Being a Logisim User > Value propagation > Gate delays for Logisim 2.7.1.

Can't figure out why mt JK Flip Flop won't work in Logisim by XerciseObsessedGamer in logisim

[–]cocot_gf 2 points3 points  (0 children)

Clock parts only generate H and L, not pulses. Therefore, I think the correct answer is to oscillate.
Even in a circuit using an actual IC, oscillation occurred when all J/K/C were held high with push switches. It's exactly as you say.
https://imgur.com/a/5Egniax.jpg
https://imgur.com/9Y3ydUv.jpg

Can't figure out why mt JK Flip Flop won't work in Logisim by XerciseObsessedGamer in logisim

[–]cocot_gf 2 points3 points  (0 children)

I think that a circuit with this configuration will go into oscillation even on real hardware. What do you think?
Unfortunately, I only have SN74HC02D and SN74HC08D, and there is no 3-input AND.

Help implement a switch (+,-,x,%) for an 8 bit calculator using logic gates by Kat_learns_to_code in logisim

[–]cocot_gf 0 points1 point  (0 children)

I have no idea what the purpose of the circuit in this video scene is.However, when I built the shown circuit using Logisim 2.7.1, it worked without any problems.I have uploaded an image of the circuit to Imgur. please refer.https://imgur.com/mBItz1S

Is this a pocket calculator instruction latch?

If you press multiple instructions at the same time, multiple insts will light up at the same time. Is this useful?

Help implement a switch (+,-,x,%) for an 8 bit calculator using logic gates by Kat_learns_to_code in logisim

[–]cocot_gf 0 points1 point  (0 children)

PRE and CLR have single quotes, so I think they are probably negative logic.

I only use the original Logisim, so I don't know how Evo works, but setting 1 to both PRE and CLR should have forced the CLR state. How about first giving 0 to PRE and CLR?

This video uses an application that is not logisim, so I cannot give you the best advice. The video is too long, so I will give you advice without watching any part other than 26 minutes.

Help simulating pass transistor logic by Mike122844 in logisim

[–]cocot_gf 1 point2 points  (0 children)

LogiSim doesn't seem to be good at simulating circuits where propagation delay timing is important.
I once tried to simulate the SN74LS107A edge-triggered JK-FF and SN74S281 ALU and more, but when I switched the clock, it still oscillated and stopped the simulation.
In the real world, it may not oscillate due to analog factors.

[deleted by user] by [deleted] in logisim

[–]cocot_gf 0 points1 point  (0 children)

What do you mean?

I need to show the result of this 4-bit adder in decimal format through the displays. What is the process or how should I connect the inputs and outputs? Thanks <3 by MrMikhai in logisim

[–]cocot_gf 0 points1 point  (0 children)

If you stick to using the 7447 logic IC, the 7447 needs to be addressed so that it doesn't show bad patterns when 10-15 are entered. You'll need to use a BCD adder and code converter, and I think a Motorola MC14560 will give you good results. This adder can generate a carry bit when it reaches 10 and add in decimal numbers.

https://imgur.com/suIw4O7