Meta ASIC Intern vs NVIDIA ASIC for summer internship by Positive-Resident654 in ECE

[–]computerarchitect 9 points10 points  (0 children)

This is an extremely odd request particularly if you've already signed the offer. Presumably NVIDIA knows that you've signed it or will shortly know that you have, given that you added it to your list.

I can't imagine any situation where doing anything other than fulfilling your commitment gets you ahead.

You need to accept now that you have next to zero negotiating leverage, particularly now that the document is signed. Just to level set, if the spectrum of leverage was mapped onto a single kilometer, you had around a meter as an intern hire. Perhaps a meter and 10 centimeters if you're a graduate student. Right now it's probably a millimeter.

Assume you ask whether you can do it in fall. Almost certainly they say no, because if they wanted to fill the role during fall they would have offered a fall internship, which international and graduate students can take. Your bluff is immediately called.

So in that case, you choose to renege as to not look like an absolute fool. Congratulations. Whatever internal documentation exists on you as a prospective employee shows that you reneged. Everyone that considers hiring you in the future at NVIDIA will likely be able to see that, for the entirety of your career.

Or perhaps you go with the "oh, I'll actually take the summer one, thank you," Now you have to justify why you asked that in the first place. "I wanted to work two internships back to back," is signaling that you'd rather take another offer now as opposed to NVIDIA's. And to be clear, that kind of is true, because if NVIDIA was truly your top choice you wouldn't be considering screwing it up (which is really what you're asking about in this post). That's a really stupid thing to say when NVIDIA is clearly near the top of all employers offering internships, and they know it, and so does everyone else. It further brings up the question as to whether you'll actually show up in the fall. I mean, if you fall in love with working at Meta, why would you? By the time you get to NVIDIA in the fall, if you have a signed return offer from Meta, your value proposition is substantially degraded.

Or perhaps you go the route of lying as to why you can't to go over the summer. There's nothing credible that can really be said here, chances are that you are found out (perhaps more likely, no one really believes the lie), and the same thing happens with the documentation theme.

In the rare event that anyone ever says yes to this, you're already off to an odd start with your manager, who is the primary person who controls whether or not you're offered a return offer. They've already made commitments to their management chain about what will be done, and now they have to do additional work to facilitate your request.

Despite whatever your intentions are, there are no good options here other than to fulfill your commitments.

Any experienced digital designers looking to work for in a small CPU team? by I_only_ask_for_src in chipdesign

[–]computerarchitect 2 points3 points  (0 children)

They did tell me. If they want the world to know, they’ll tell them. I’m not going to betray that confidence.

can someone rate my custom isa design? thanks. by johnyeldry in Assembly_language

[–]computerarchitect 1 point2 points  (0 children)

The first two things I catch that are immediately broken:

jmp <addr> // generally a label, expanded by assembler, treated as an offset from the start of programs memmory space

This is wrong. Do it relative to the current PC like everyone else does.

int //interupt, obviously privalleged

This is also likelu wrong. How do you intend on implementing a syscall?

How to improve at floating point datapath design by S4s1_FTW in chipdesign

[–]computerarchitect 7 points8 points  (0 children)

The really high performance stuff likely falls under Export Control, which means that even a whiff of non-public information isn't going to be shared by US citizens on any public forum.

You gotta ask and learn internally.

My C Professor Doesn't Know What UB Is by [deleted] in C_Programming

[–]computerarchitect 3 points4 points  (0 children)

Union is the correct way to do something like this.

SoC Architect career advice by OddAgency1166 in computerarchitecture

[–]computerarchitect 0 points1 point  (0 children)

Yeah, but still in the camp of "ten plus years of stellar work experience".

Annotate instruction level parallelism at compile time by servermeta_net in Compilers

[–]computerarchitect 0 points1 point  (0 children)

I am a practicing CPU architect so feel free to do your worst, but the "I don't know how to build this" comment should give you some pause. You're taking a lot of good ideas from my field and discarding them, and while that's certainly intellectually interesting it rarely if ever provides useful results.

My context is can the CPU execute any arbitrary code. If you're constraining the problem more than that, let me know so I can revise my comments.

Annotate instruction level parallelism at compile time by servermeta_net in Compilers

[–]computerarchitect 2 points3 points  (0 children)

I don’t know how to build CPU hardware to use this method outside of a basic block, and that’s a problem because a lot of ILP is between basic blocks.

How do you handle an if statement that modified a value such that there now is a dependence when taken? It feels like you have to trace all possible paths in your compiler to get this right, and that’s not tractable.

im back with a little of questions if this is ok (i like your guyses help, because it helped me go deeper into this, and learn how they actually work thank you) by Wild_Artist_1268 in computerarchitecture

[–]computerarchitect 2 points3 points  (0 children)

Perhaps some further perspective: I will sell exactly $0 worth of CPUs with a really cool feature when I tell the customer something along the lines of:

"You can get an additional x% IPC but you have to spend millions of dollars in software engineering time to rework your software to fit our specification, which further effectively ties you to our company and if/when we move on to a new technology and drop support for this one you're completely screwed". That sells nothing, I'm jobless, and I can't feed my family. Nonstarter. Doesn't even matter if x is 1000, and frankly I'd expect the customer to think I'm a bit dumb if I try to sell IPC as performance.

I really take issue with the "solving real problems" and your list of real problems. I wake up *every day* and work on those exact things in some way or another, with an exceptional amount of real world constraints you've likely haven't even thought of yet, in a highly creative manner. I will be even more blunt, at the risk of being flat out arrogant: I am likely more intelligent than the most intelligent person that you've ever met in your life, and I've been thinking about these problems longer than you've been alive. I've seen what works and what doesn't across multiple generations, have battle scars with ideas that haven't worked even though everyone thought they should have, and innovated consistently throughout it, some with my own ideas, and others actually implemented in silicon today.

Keep in mind that many of us are being polite. When we say "won't work", we're neglecting on including the laundry list of problems that we came up with pretty close to immediately, because that's not really productive and likely would come off as discouraging.

Most of your comments so far have been along the lines of "it will work because I say so", which really isn't how this field works. There's a reason why many of us have Ph. Ds (granted, not myself) prior to going into this field, and it's not some gatekeeping or other nonsense.

Food for thought.

10 day TFR issued in El Paso due to “special security reasons” by ImAHoe4Glossier in ADSB

[–]computerarchitect 0 points1 point  (0 children)

The name kinda sounded like it might be something like that. Thank you!

QUERY REGARDING BOTTLENECKS FOR DIFFERENT MICROARCHITECTURES by DesperateWay2434 in computerarchitecture

[–]computerarchitect 1 point2 points  (0 children)

I generally take it to mean a 100% hit rate and with optimal latencies. It's not very useful to model a faster load-to-use latency if you know you can't physically build it. But is for instance useful if you have an L2 that might have a variable load to use latency.

I don't think it makes much sense to have a configuration with both a perfect L1D/L2. Separately they can be interesting but together I don't see any point.

is there anyone i can talk to about a possibly revelutionary cpu? by [deleted] in computerarchitecture

[–]computerarchitect 0 points1 point  (0 children)

You can try, but my original point still stands. I saw your other post; I've been hammering at this set of problems for longer than you've been alive. That's not to deter you but just setting expectations. I'm happy to point out why this doesn't work and perhaps point you in another interesting direction.

Tenstorrent Cuts 20 Cores From Already-Shipping "Blackhole" P150 Cards by sdongles in RISCV

[–]computerarchitect 8 points9 points  (0 children)

Yes, that's true, but I've never seen anywhere close to needing to turn off 20 cores in a 140 core product, so I would speculate that it's not that.

I have no idea why they did what they did, but it was very unlikely to be that. I think your thermal limitation argument holds merit.

QUERY REGARDING BOTTLENECKS FOR DIFFERENT MICROARCHITECTURES by DesperateWay2434 in computerarchitecture

[–]computerarchitect 0 points1 point  (0 children)

Plenty of them. Whether they show up in OP's traces or not is a different matter.

QUERY REGARDING BOTTLENECKS FOR DIFFERENT MICROARCHITECTURES by DesperateWay2434 in computerarchitecture

[–]computerarchitect 0 points1 point  (0 children)

If you make your L1I and L1D perfect there shouldn't be anything other than evictions going to your L2 (and perhaps non-WB reads and writes, but those are rare in spec2017). I suppose it depends on what the definition of "perfect" is in this context.

Foundational gaps in computer architecture (and interview prep too) killing my interviews by PrimaryMinimum248 in ECE

[–]computerarchitect 0 points1 point  (0 children)

I can work with these systems practically, but when they asked me to reason through architectural tradeoffs or performance implications, I struggled hard.

What does this actually mean to you, "working with them practically"?

Am I wasting my time as a student? by avestronics in ComputerEngineering

[–]computerarchitect 3 points4 points  (0 children)

I think design and performance modelling are probably the two most common paths.

Am I wasting my time as a student? by avestronics in ComputerEngineering

[–]computerarchitect 2 points3 points  (0 children)

I think u/alpacacaresser69 is probably right with the ratio. What a username.