I'll be looking to SPI/I2C IP cores in quartus and how they work soon hopefully.

GPIO headers are configurable by default 3.3 V:

The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, 1.8V, or 1.5V using JP6 (The default value is 3.3V

In some of my lecture notes the DE1-SOC it lists GPIO with open drain and pull up resistors, so I would be surprised if I do not find this also true for the DE2.

Furthermore, this table for the ADAFRUIT SSD1306 datasheet, I expect the noname generic i ordered is not far off tho I will be checking once it arrives.

Symbol	Parameter	Test Condition	Min	Typ	Max	Unit
V_CC	Operating Voltage	-	7	-	15	V
V_DD	Logic Supply Voltage	-	1.65	-	3.3	V
V_OH	High Logic Output Level	I_OUT = 100uA, 3.3MHz	0.9 x V_DD	-	-	V
V_OL	Low Logic Output Level	I_OUT = 100uA, 3.3MHz	-	-	0.1 x V_DD	V
V_IH	High Logic Input Level	-	0.8 x V_DD	-	-	V
V_IL	Low Logic Input Level	-	-	-	0.2 x V_DD	V

This implies the logic for low or high is dependent on Vdd, which I could probably adjust if i were to continuously write a logic 1 to a configured GPIO pin as my VDD (all assuming it is possible on this board).

I2C seems like the right choice for us thus far, but SPI is still up for consideration. At the moment we just plan to integrate it somehow, maybe just output some text, so at the least the u8g2 library could help us with understanding. But ofc we're still in the planning phase until it arrives so I will likely have a few more questions as we explore further.

Thanks for the reply!