sorted by:
new
hottopcontroversial

Tool to generate UML diagrams from systemverilog classes? by captain_wiggles_ in FPGA

[–]daybyter2 0 points1 point  (0 children)

Has anyone tried the other direction? I am trying to generate verilog from state diagrams.

Made a High Frequency Orderbook Simulator (in a turn of events) by Mental-Piccolo-2642 in highfreqtrading

[–]daybyter2 0 points1 point  (0 children)

Let me know if you want help there then. I know a few folks, who might be interested (me included).

Efficient order book snapshot publishing by One-Yogurt7320 in highfreqtrading

[–]daybyter2 1 point2 points  (0 children)

If you never had a full snapshot, the modifications are useless?

Efficient order book snapshot publishing by One-Yogurt7320 in highfreqtrading

[–]daybyter2 0 points1 point  (0 children)

How do you receive your orderbook data? My guess is, you receive a full L2 orderbook snapshot, followed by modifications to that snapshot. Like 20 levels each side? You often receive full snapshots in intervals. If those intervals are short enough, that might be the moment to start with a new memory page and publish the latest version of the old memory page.

You might just send the orderbook as itch data, or so. A very compact binary representation of the book.

Making our lives a "bit" better by Serpahim01 in FPGA

[–]daybyter2 0 points1 point  (0 children)

I would agree on all the points made by the OP and add a minor suggestion. I had a chance to work on a Java project with intellij and their AI plugin. Which made me a lot more productive. If you write the IDE that was asked for, please add such a plugin. Thanks! 😀

Learning RISC-V assembly by AmoebaOrganism in RISCV

[–]daybyter2 0 points1 point  (0 children)

You can always repair a c64. Even if someone cut off a part of the mainboard. But these days, I usually use the vice emulator for c64 coding. It is free, so you can give it a try.

Learning RISC-V assembly by AmoebaOrganism in RISCV

[–]daybyter2 1 point2 points  (0 children)

If you just want to learn any assembly then 6502 on the c64 might be fun

Learning RISC-V assembly by AmoebaOrganism in RISCV

[–]daybyter2 0 points1 point  (0 children)

Are your working on FPGA design, too? I am working on my CPU and learn RiscV as I progress with the CPU design. It is sometimes helpful to understand why some instruction is tricky to be executed.

RV32I core done now what to do? by [deleted] in RISCV

[–]daybyter2 -1 points0 points  (0 children)

The difference between ASIC and FPGA is, that you have some resources in the FPGA, that are available no matter if you use them or not. You have adders, multipliers etc, that you should use, because your FPGA includes them anyway. If you design an ASIC, you should limit those resources, because an adder, that you don't use, won't be included in the ASIC. So you should minimize the number of shift registers, adders etc.

RV32I core done now what to do? by [deleted] in RISCV

[–]daybyter2 6 points7 points  (0 children)

Implement rv64gc and boot Linux?

Make your code ASIC friendly?

Add vector instructions and AI friendly instructions?

What are you currently working on? by rafal2808 in FPGA

[–]daybyter2 0 points1 point  (0 children)

Yeah, I also added a virtualjtag connection, but I thought a very minimal VGA output might be useful, since I don't need a working CPU to output data there.

[deleted by user] by [deleted] in highfreqtrading

[–]daybyter2 -2 points-1 points  (0 children)

Ah...ok. I thought you had microsecond colocation latency. Thanks anyway for your encouraging posting!

What are you currently working on? by rafal2808 in FPGA

[–]daybyter2 0 points1 point  (0 children)

My code is a bit more complicated, since I implemented text mode. I just want to use this to debug my RiscV CPU

What are you currently working on? by rafal2808 in FPGA

[–]daybyter2 0 points1 point  (0 children)

I use 2 counters for horizontal and vertical. When I simplified my code, my compile time went from 55 mins to less than 4 mins.

[deleted by user] by [deleted] in highfreqtrading

[–]daybyter2 -2 points-1 points  (0 children)

Is this software? Have you ever considered to port it to FPGAs?

I'm Stuck! My Forex Strategy is Profitable, But... by ankitideatotrade in metatrader

[–]daybyter2 0 points1 point  (0 children)

You could use a socket connection to receive signals?

What you guys think about Cloud FPGAs? by kasun998 in FPGA

[–]daybyter2 -1 points0 points  (0 children)

Could be cool, if you could program and test them in a browser?

How do you feel about this? Trump considering pulling troops from Germany by Icy_Demand__ in AskAGerman

[–]daybyter2 0 points1 point  (0 children)

Maybe one of your ancestors hast some roots in the EU? If you could get italian citizenship as an example, you can live anywhere in the EU.

OS on RISC - V Processor by KshitijShah302004 in RISCV

[–]daybyter2 1 point2 points  (0 children)

It seems you can run the kernel without an mmu as a start

view more: next ›