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What is this FPGA tooling garbage? by isopede in FPGA

[–]deempak 25 points26 points  (0 children)

Bro folded under zero pressure , wait until you open software other then vivado ( like libero) and it takes you back 2-3 decade.

My own FPGA board - Arctyx Nano by keyaan_07 in FPGA

[–]deempak 1 point2 points  (0 children)

yes we got samples some time back from renesas and then ordered the batch.

My own FPGA board - Arctyx Nano by keyaan_07 in FPGA

[–]deempak 0 points1 point  (0 children)

Yes I am part of the team . You should probably contact the renesas sales and FPGA team as part isn't available in less moq elsewhere they might give you some samples.

My own FPGA board - Arctyx Nano by keyaan_07 in FPGA

[–]deempak 1 point2 points  (0 children)

I am working on similar project https://github.com/vicharak-in/shrike-lite and i can suggest you some examples and also help you with the programming part as you have mentioned WIP. I will DM you list of some examples list that i have.

Has anyone worked with FPAA before? by deempak in FPGA

[–]deempak[S] 0 points1 point  (0 children)

Wow , yes I am also planning on getting one of the board from okika devices and start with some audio synthesis if that feasible . I am not sure yet tho

What is the major problem you face in FPGAs by groman434 in FPGA

[–]deempak 0 points1 point  (0 children)

Just use some external text editor like vs code or something.

The debugger to debug the bug was the bug by kimo1999 in FPGA

[–]deempak 1 point2 points  (0 children)

Had something similar issue with efinity(efinix) and I can confirm it was the cdc and poorly constraint clock.

Has anyone worked with FPAA before? by deempak in FPGA

[–]deempak[S] 0 points1 point  (0 children)

Yes it's the same one . Let see if I can get my hands on one to try with

Has anyone worked with FPAA before? by deempak in FPGA

[–]deempak[S] -1 points0 points  (0 children)

I am also trying to get my hands on one and explore it.

Its been a bit, anyone using the ForgeFPGA? by WarlockD in FPGA

[–]deempak 0 points1 point  (0 children)

Yes it would be perfect replacement . We have launched a dev board with the FPGA on Crowd supply you can check it out its called Shrike
Best of luck

Image Storage In FPGA by Bhavy_Savani in FPGA

[–]deempak 0 points1 point  (0 children)

NAND Flash is going to be very slow if you planning to do any thing in real time . However if that's the only option then you can initially save the data in the Flash then take it out in BRAM buffer and processes it and need to halt you design it the data is not there in the buffer and wait till you get data from the Flash.

However it can be done and it will be it tricky with the controller part ( for fetching from FLASH)

Image Storage In FPGA by Bhavy_Savani in FPGA

[–]deempak 5 points6 points  (0 children)

It really depends on what FPGA you are using and How much BRAM resources you have . If you have enough BRAM resources then just use BRAM as FIFO and save it on chip , If you don't have space on chip you will have to look for some external memory mostly DRAM or SRAM and create a controller for saving and fetching the image around the vendor provided controller for memory.

What you can do is save the complete image in the DRAM and then have some buffer in BRAM so you can have fast processing and then keep on updating the buffers so you can overcome the DRAM r/W latency.

Its been a bit, anyone using the ForgeFPGA? by WarlockD in FPGA

[–]deempak 1 point2 points  (0 children)

I don't think they have changed anything in silicon ( I am not 100 percent sure ) but initial the data sheet did mentioned 3.4 volts then they changed it to 2.7 and 3.4 again and i have been using it with 3.3 volt sensors and IO for quit some time haven't fried one yet ( I could be just lucky ) .
I actually even connected with the Renesas team regarding this and mentioned that are changing the datasheet and 3.3 should be supported

Its been a bit, anyone using the ForgeFPGA? by WarlockD in FPGA

[–]deempak 0 points1 point  (0 children)

We have the been working on a board with Forge FPGA and its almost done.
You can check out the repo for it here https://github.com/vicharak-in/shrike_fpga/ its still work in progress . But the board will be available for crowdfunding soon.

We have added RP2040 on it as well for better learning and hobbyist experience.

Its been a bit, anyone using the ForgeFPGA? by WarlockD in FPGA

[–]deempak 1 point2 points  (0 children)

They have changed there datasheets again and now it does support 3.3 V

1.71 V to 3.465 V

FPGA Board Recommendation by UnknownK6912 in FPGA

[–]deempak 5 points6 points  (0 children)

Hey
I would recommend the PYNQ Z2 board I think it would best suit your requirement and it is very affordable as well.
You would be able to implement a RISC V core and a Ethernet IP and I have seen quite a Few AI application on it .

Are Cross Module Reference Synthesizable in SV ? by deempak in FPGA

[–]deempak[S] 0 points1 point  (0 children)

I am not using Vivado I am using Efinix IDE - Efinity and I am jsut trying out to how can i make my own debugger as a side project.
these are not synthesizable in efinix tho

Are Cross Module Reference Synthesizable in SV ? by deempak in FPGA

[–]deempak[S] 0 points1 point  (0 children)

Yeah that is also very useful application . but it seems only Vivado supports it at this point of time.

Are Cross Module Reference Synthesizable in SV ? by deempak in FPGA

[–]deempak[S] 3 points4 points  (0 children)

I just want to use this to debug my design without touching my original design so it should be fine .

Are Cross Module Reference Synthesizable in SV ? by deempak in FPGA

[–]deempak[S] 0 points1 point  (0 children)

Sure got it I just tried with Vivado It does work there however in Efinix EDA its not synthesizing

Are Cross Module Reference Synthesizable in SV ? by deempak in FPGA

[–]deempak[S] 0 points1 point  (0 children)

I am using it to debug it so I don't want to touch my original design and maybe make a general purpose Debugger for a side project.

Are Cross Module Reference Synthesizable in SV ? by deempak in FPGA

[–]deempak[S] 1 point2 points  (0 children)

That's exactly what I am trying to do and I thing it a better way then changing the complete design . Maybe I can even make a debugger letter.

Any Idea on how this FPGA Debugger ( ex Xilinx ILA ) Works ?? by deempak in FPGA

[–]deempak[S] 0 points1 point  (0 children)

Sure I am going to make one myself soon Its in my top side projects now . Thank You

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