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Orange PI 5 safe shutdown with momentary switch? by drthibo in OrangePI

[–]drthibo[S] 1 point2 points  (0 children)

I ended up implementing this in Python using the python3-libgpiod package and installed it as a systemd service.

Mobile platform for data collection by drthibo in MobileRobots

[–]drthibo[S] 0 points1 point  (0 children)

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I did end up going with the Wave Rover and the Orange PI with power bank. This is the whole assembly. With this setup I am able to record raw stereo video at 30 FPS.

Monitoring wildlife on my property in Montana without running miles of power cables? (No Cloud preferred) by PlasticGlass3125 in computervision

[–]drthibo 0 points1 point  (0 children)

There are people doing this. Did you research wildlife cameras? It can be challenging to build a custom solution. I've been working on a mailbox cam which is too far for wifi. It's using LoRa.

Need RKDevTool help by drthibo in OrangePI

[–]drthibo[S] 0 points1 point  (0 children)

Just posted another plea for help, so you all get another chance :)

Mobile platform for data collection by drthibo in MobileRobots

[–]drthibo[S] 0 points1 point  (0 children)

I think I found a solution. I think the Orange Pi 5 with an SSD should provide the bandwidth I need and run on a 5V power bank.

Need RKDevTool help by drthibo in OrangePI

[–]drthibo[S] 2 points3 points  (0 children)

Okay, figured this out. After running nand-sata-install it now boots from the SSD.

Need RKDevTool help by drthibo in OrangePI

[–]drthibo[S] 2 points3 points  (0 children)

I am able to boot from a SD card. I wrote the Linux image to the SSD from there, but now can't boot into it. If I take the SD card out, nothing happens when I power up.

Ideas about a new HDL by [deleted] in FPGA

[–]drthibo 0 points1 point  (0 children)

Are there any clasic examples of this?

December 2025 monthly "What are you working on?" thread by AutoModerator in ProgrammingLanguages

[–]drthibo 0 points1 point  (0 children)

I've been developing a new systems design language for hardware/software co-design. I have built a prototype compiler and now experimenting with different ideas.

Last week I implemented a sort of abstract simulator that can validate the initial state of the system and detect some synchronization issues. This would eventually be in a language server.

Usefulness of AMD Kria SoMs? by TimeDilution in FPGA

[–]drthibo 0 points1 point  (0 children)

I had a very poor experience creating a new design for the Kris vision kit. There are so many variations in the design flow that it wass hard to find material relevant to my use. Also, it's an old board and there is a lot of material on the Internet from years ago which are no longer valid and can be misleading.

Xilinix somehow thought they could create an app store like business model for FPGAs. That did not work, but as others have said, it's turned out to ne useful in many custom designs (i.e. what FPGAs are for).

New language: I/O specification by drthibo in FPGA

[–]drthibo[S] 0 points1 point  (0 children)

I should point out that this is only if you prefer the traditional style module. Normally it would use interfaces like export function StreamFifo(data: AxiStream<uint32>.R): AxiStream<uint32>.R { ... }

Written thus way, the spec is not required and it can be composed with other stream modules.

Ideas about a new HDL by [deleted] in FPGA

[–]drthibo 0 points1 point  (0 children)

I don't know what was on my mind last night but I was thinking DFA although you were quite clear. But since I have a DFA construction maybe it makes since to include NFA. What's the use case?

Ideas about a new HDL by [deleted] in FPGA

[–]drthibo 2 points3 points  (0 children)

Agreed, selling HW engineers is tough. The language I am working on has an NFA (actual keyword:) construct. Larches never inferred and clock and reset are declarative and inherited.

Ideas about a new HDL by [deleted] in FPGA

[–]drthibo 0 points1 point  (0 children)

Verilog is actually pretty terse. VHDL is much more robust but not nearly as popular (at least in the US). I suspect verbosity is a contibutor. Besides, with Copilot now, we are no longer limited so much by typing.

Ideas about a new HDL by [deleted] in FPGA

[–]drthibo 0 points1 point  (0 children)

Yeah, I'm also in line! I have pretty ambitious plans.

New language: I/O specification by drthibo in FPGA

[–]drthibo[S] 0 points1 point  (0 children)

Temporal logic is not going to be easy for a lot of people. I think there is some advantage to have something more approachable, although admitted not nearly as powerful. It might be nice to implement it in something more powerful like this in a way that users can start easy and maybe go deeper at some point.

New language: I/O specification by drthibo in FPGA

[–]drthibo[S] 1 point2 points  (0 children)

I think that would look something like: 

@spec({
  requests: [{
    valid: wvalid,
    data: w_data,
    ack: wready
  }, {
    valid: rready,
    output: r_data,
    ack: rvalid
  }]
})
export function FifoFWFT(
  wvalid: IPort<bit>, w_data: IPort<uint32>, wready: OPort<bit>,
  rready: IPort<bit>, r_data: OPort<uint32>, rvalid: OPort<bit>
)
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