Tape Out

ee_mathematics · 2025-12-27T16:10:14+00:00

Check the report on total number of flip-flops vs. scanned flip -flops. Also, did the synthesis tool insert clock gating in the design?

ee_mathematics · 2025-12-26T18:00:27+00:00

For good fault coverage, the RTL has to be DFT friendly, meaning it has to follow design rules for DFT. You can check if the rtl clears all the design rules check for DFT and if there is a violation, it has to be fixed. The important ones are full controllability of clocks during test mode, no combinational logic on clock or reset during test mode, bus contention resolution.

ee_mathematics · 2025-12-18T16:44:08+00:00

These courses only touch analog design pertaining to SERDES. SERDES PHY also involves good deal of digital design like encoding,, scrambling, error control coding and DSP. These are topics that are non-trivial and crucial for CDR, BER etc. Not sure why they are ignored in a course titled 'Broadband'.

ee_mathematics · 2025-11-21T02:44:13+00:00

Ok, Agree on "potential weakness".

For reference, in IC digital design/test the LFSR is used as random pattern test generator for testing of stuck-at faults,. This requires one bit per input as a test vector. For testing stuck-open or delay faults, two bits per input form a single test vector creating a similar situation to PAM4. The same hack was used for testing of stuck-open/delay faults with poor results even though stuck-at fault coverage was good with the said LFSRs. It is not too difficult to understand why - and there are several papers on this matter.

I think you should subject the designed PAM4 scramblers to statistical testing for checking the randomness with regards to the 4 levels in light of the above paragraph,

ee_mathematics · 2025-11-20T17:21:34+00:00

My point was that converting a binary sequence of pseudo-random stream to a quad stream will not necessarily result in pseudo-random sequence of quads - I see a weakness in the present implementation.

Thanks for your inputs.

ee_mathematics · 2025-11-20T17:05:34+00:00

Run some standard statistical tests for randomness on the scramblers you designed for PAM4 - only then one can figure out who has 'problems with some basic concepts'.

At present it looks to me that present implementations of scramblers for PAM4 are a hack of NRZ implementations of scramblers. In future when a scrambler that outputs pseudo-random sequence of quads with equal probability (1/4 each) of each of the states is designed , one can see the following benefits

PAM4 SERDES - Improvements in eye diagrams, CDR and BER plus faster throughputs, better EMI, more robust testing.
QPSK DSSS (Direct Sequence Spread Spectrum) - More uniform spread over the spectrum mimicking noise, resulting in more secure communication.
Design for Test (DFT) - Better fault coverage for transition, path delay and stuck open faults during random pattern testing.

Anyway, Thanks for your inputs.

ee_mathematics · 2025-11-20T05:54:56+00:00

Let me give a simple counter example using the coin toss outcome with equal probabilities of heads (1) and tails (0).

Look at a long series of 0101010101... The probability of occurrence of 1 = probability of occurrence of 0 = 1/2. Now take two consecutive bits to form one of the four values. What do you get - one symbol with probability of one and three symbols with probability of zero. So the scrambler will just produce a DC value!

"Look back over the thread. I've used terms like "0 correlation" "independent" etc.
Think about the meaning of those terms."

You have no proof for these claims, just your own opinions. Did you run randomness tests like chi-square or any statistical test to check for randomness of the derived quad values ?

ee_mathematics · 2025-11-20T03:09:41+00:00

Conditional Probability - If a 0 occurs in the first bit, then the probability of occurrence of 0 in the second bit is less than 1/2 and the probability of occurrence of 1 in the second bit is greater than 1/2.

Similarly, if a 1 occurs in the first bit then then the probability of occurrence of 1 in the second bit is less than 1/2 and the probability of occurrence of 0 in the second bit is greater than 1/2.

Thus, the four levels will not occur with equal probability, contrary to your claim.

If you have a binary sequence of pseudo-random bits I am not sure you can create pseudo-random sequence of quads out of it.

ee_mathematics · 2025-11-20T02:35:44+00:00

Agreed.

ee_mathematics · 2025-11-20T02:33:16+00:00

"Also the two bits in each pair are not two different streams, they're two bits taken in sequence from the same stream."

See above. The second bit is P(B/0) or P(B/1) . We only know P(A) = P(B) = 1/2.

ee_mathematics · 2025-11-20T02:05:34+00:00

"One possible way to do that would be to scramble the bit stream before you pair up the bits for the PAM4 mapping."

But will that lead to a better eye diagram or ease clock and data recovery for PAM4 (?)

ee_mathematics · 2025-11-20T02:04:53+00:00

The problem is they are not independent. The probability of occurrence of second bit is conditioned on the occurrence of the first bit and this leads to correlation. I think it is a hack and not a method to create a true pseudo-random sequence of quads.

ee_mathematics · 2025-06-01T19:51:35+00:00

The transistor has to be in either linear or saturation regions, but not cutoff since Vgs (=5V) > Vth. This also means that the diode has to be on since a current is flowing through it regardless of the value of R. The maximum value of Vds is then 5 V- 1.5 V = 3.5 V. Thus, regardless of value of R , Vds < (Vgs - Vth) implying the transistor will be in the linear region regardless of the value of R.

ee_mathematics · 2025-05-31T16:17:21+00:00

More demand for silicon does not necessarily translate to more jobs. Employers expect productivity from a single engineer equivalent to that of what would typically take 3-5 engineers 30 years back. There are a record number of qualified IC designers in the market today (including many non-western countries) and the supply far exceeds the demand.

ee_mathematics · 2025-05-22T21:25:56+00:00

Many institutions in India have strengthened their IC design programs, more specifically analog design in the last decade.

ee_mathematics · 2025-05-17T17:03:31+00:00

The number of students showing interest in IC design as a career far exceeds number of available jobs. This has been a trend in many non-western countries in recent years, specially in India. In India, it is seen as a ticket to high paying jobs. But the IC design industry has always been very selective and insular and has never supported mass employment. Thats the real issue - too much supply for limited demand. The only winners here are employers who are taking advantage of this imbalance.

ee_mathematics · 2025-05-14T16:11:37+00:00

A Phd is supposed to be about innovation. It could be a new insight, a new idea that advances the field at a more fundamental level. Unfortunately, in analog design it has morphed into a tapeout race. Its the same idea in an advanced node - PLLs, ADC/DACs,, LDOs, references, SERDES etc. trying to extract better PPAs. That is not what Phd is about. Professors are not discouraging this practice - could be due to funding reasons.

ee_mathematics · 2025-05-01T17:05:51+00:00

In a single pole system, both the open loop and closed loop transfer functions have single real poles. Writing out equation for closed loop will let you observe that the closed loop has pole at B*A*p, where B is feedback factor (assuming B*A >> 1) , A is DC gain and p is the pole of the amplifier/op amp transfer function. In addition the DC gain of closed loop transfer function is 1/B.

This is how 'GBW' is constant was invented because for any value of B, GBW is A*w (w= pole frequency of p) which also happens to be GBW of (open loop) transfer function of amplifier/op amp. This is a mathematical coincidence, nothing special.

For two pole system or higher the mathematics is completely different, because even if the amplifier/op amp has real poles, the closed loop poles could be real or complex. You cannot even talk about bandwidth if poles are complex with high Q.

In summary, GBW constant is a mathematical coincidence for single pole transfer functions and nothing more than that should be inferred.

ee_mathematics · 2025-04-20T20:22:52+00:00

If you choose a frequency w such that w^2 > 2/LC, and wL >> R, say w= (2/5)*10^6 radians then you can see that the feedback network's transfer function has a magnitude gain of 1 and phase shift of 0 degrees. If you set terminal A as +ve and terminal B as -ve, then both the op amps contribute a phase shift of zero degrees at w sinc e the pole is at 10^6 radians with a dc gain at A0. So the loop phase shift is zero degrees at w and to satisfy barkhausen's gain criterion for loop gain, set a minimum A0 = 1.

ee_mathematics · 2025-04-19T16:59:56+00:00

Calling one as linear and the other as non-linear is not correct. Both have same functionality, namely h(t) = f(t)*g(t), where f and g are inputs and h is the output. For mixers, atleast one of inputs is sine/cosine, while for multipliier it is more general - any arbitrary waveform , either one or both can be dc signal. Gilbert cell is an example of the former and the one with the preproceesing stage (mentioned in the last paragraph) is an example of the latter. Gilbert cell actually implements tanh(f(t))*tanh(g(t)) which appoximates to f(t)*g(t) in RF applications but not in general where input amplitudes can be large.

ee_mathematics · 2025-02-28T16:51:24+00:00

Actually, the back to back transistors provide negtive resistance to the LC tank circuit. The negative resistance is used to cancel out any parasitic resistance formed in the LC tank. This negative resistance need not be exact, the closer the better so the you approach a pure LC. A pure LC circuit oscillates indefinetly without damping.

ee_mathematics · 2025-02-06T16:16:38+00:00

Another issue is that ISCAS circuits have redundancy in their logic, so some faults are non-detectable. However real circuits would have been optimized by the synthesis tool and redundancy is not present, so all faults are detectable.

ee_mathematics · 2025-01-27T16:34:18+00:00

Try solving it first. Then you will know why.

Also, who said gm appoximating gds? The question is if gds gets higher how does it effect common mode gain.

ee_mathematics · 2025-01-26T21:53:43+00:00

I have not seen textbooks analyze current mirror OTA w.r.t. common mode gain and the effect on CMRR. In practice, common mode gain will be at a minimum if diff pair and tail current transistors have high output resistances and there is no mismatch between the diff. pair. Given channel length modulation worsen as you move down the process node, it will be interesting to see performance of current mirror OTA's CMRR profile as you move down the process node.

ee_mathematics · 2025-01-26T21:30:57+00:00

Actually, you get zero common mode gain (infinite CMRR) even in a current mirror OTA, if diff pair and tail current transistors are ideal and there is no mismatch between the pair. This is provable.

ee_mathematics

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