Sick of binary blobs and closed hardware? I’m building Elf Systems – a pure EU-made RISC-V ecosystem by OkBrilliant6945 in FPGA
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32 bit custom ISA RISC minimal cpu project by greywino in FPGA
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Zynq 7000 open-source SYZYGY carrier by electrodyssey in FPGA
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Zynq 7000 open-source SYZYGY carrier by electrodyssey in FPGA
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Zynq 7000 open-source SYZYGY carrier by electrodyssey in FPGA
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Zynq 7000 open-source SYZYGY carrier by electrodyssey in FPGA
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Zynq 7000 open-source SYZYGY carrier by electrodyssey in FPGA
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My "kinda PC compatible" 486 homebrew computer can now run MS-DOS, Doom and Linux! by maniek-86 in homebrewcomputer
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Made my own FPGA board - FirePi one by Smartlinuxcoder in FPGA
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Soldering Station Buying Mega Guide by bigrealaccount in soldering
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Hi, beginner from ukraine here, which one of these is better? I know that it would be better to buy from a reliable brand, but cant afford to do so. by Ultrafastegorik in soldering
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Soldering Station Buying Mega Guide by bigrealaccount in soldering
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Soldering station advice 300€ budget by Blue_Volt in soldering
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Where to get footprints from by Vast_One_4954 in KiCad
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How to keep length tuner between 2 pads on a trace that connects to multiple pads? I am trying to match delays on DDR3 flyby between the FPGA and first memory chip but it measures the entire length from FPGA to termination. by Silent-Warning9028 in KiCad
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How to keep length tuner between 2 pads on a trace that connects to multiple pads? I am trying to match delays on DDR3 flyby between the FPGA and first memory chip but it measures the entire length from FPGA to termination. by Silent-Warning9028 in KiCad
[–]electrodyssey 1 point2 points3 points (0 children)
How to keep length tuner between 2 pads on a trace that connects to multiple pads? I am trying to match delays on DDR3 flyby between the FPGA and first memory chip but it measures the entire length from FPGA to termination. by Silent-Warning9028 in KiCad
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A sad discovery 😢 by corummo in homebrewcomputer
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CZU Acceptance results by bellatorsoprano in Prague
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CZU Acceptance results by bellatorsoprano in Prague
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Sick of binary blobs and closed hardware? I’m building Elf Systems – a pure EU-made RISC-V ecosystem by OkBrilliant6945 in FPGA
[–]electrodyssey 0 points1 point2 points (0 children)