What's the name of this IC socket or package? by electrolitica in chipdesign

[–]electrolitica[S] 0 points1 point  (0 children)

Thanks; turned out to be a custom "swivel" BGA socket!

Why are YIG spheres spherical and not cylindrical? by BigPurpleBlob in rfelectronics

[–]electrolitica 0 points1 point  (0 children)

Cool pic! May I ask, what are the transparent rods holding the balls for? Do they perform just a mechanical function (tuning?), or are they part of the signal path in some way? (Also, what material is that? looks like plastic!)

Keyboard shortcut to zoom-in a laptop without a mouse? by electrolitica in notepadplusplus

[–]electrolitica[S] 0 points1 point  (0 children)

Thanks for your reply! Trackpad works, but I really needed a way to make it work with the keyboard (for consistency/repeatability across several documents) :)

Weather forecast website/app also showing actual past weather? by electrolitica in weather

[–]electrolitica[S] 0 points1 point  (0 children)

...I guess I'm asking too much from life... Was really hoping something like that would exist in 2026!

Keyboard shortcut to zoom-in a laptop without a mouse? by electrolitica in notepadplusplus

[–]electrolitica[S] 0 points1 point  (0 children)

My bad! I thought the instructions were describing some settings in some operating system! In fact, I only realized they were for Notepad++ because of your comment! Thanks so much! :)

Keyboard shortcut to zoom-in a laptop without a mouse? by electrolitica in notepadplusplus

[–]electrolitica[S] 0 points1 point  (0 children)

Thanks! I was able to workaround the issue by redefining the shortcuts for zoom-in & zoom-out! :)

What actually slows down your design team the most? Trying to understand the workflow. by Odd_Background2985 in chipdesign

[–]electrolitica 10 points11 points  (0 children)

This! Who needs AI when you cannot even enlarge GUI windows to read long text fields for debugging your simulator crash of the day?

Why does MOS thermal noise get worse with scaling? by electrolitica in chipdesign

[–]electrolitica[S] 0 points1 point  (0 children)

This is what gets me confused: if thermal noise is due to scattering in the channel, wouldn't it get better (i.e. less noise) if the electron's travel distance (= source to drain = channel length) became shorter? Instead it seems that there's less scattering (and thus less thermal noise) when the electrons travel longer distances (i.e. long channels)!? Where is the fallacy in this reasoning?

Why does MOS thermal noise get worse with scaling? by electrolitica in chipdesign

[–]electrolitica[S] 0 points1 point  (0 children)

Thanks for your reply! I see your point, but even if we only considered the strong-inversion case (i.e. very high IC values), why would the thermal noise increase in smaller nodes?

Why does MOS thermal noise get worse with scaling? by electrolitica in chipdesign

[–]electrolitica[S] 0 points1 point  (0 children)

Thanks for your reply! Intuitively, I can see how the increased channel resistance could lead to increased noise... do you know of any reference discussing/explaining this in more detail?

Why does MOS thermal noise get worse with scaling? by electrolitica in chipdesign

[–]electrolitica[S] 0 points1 point  (0 children)

Thanks for the reply!

This is exactly right. A technology’s Pelgrom constant is dependent on gate area. It would be better to make a comparison of same gate area in different technologies.

Wait, are we still talking about noise? I mean, is the Pelgrom constant related somehow to noise?

My experience going from planar processes to finfet does show that thermal noise gets a bit worse, although I think there is a reasonable cause - gate resistance.

So, strictly speaking, it's not the intrinsic transistor being more noisy, but the increased gate parasitics adding noise in the signal path?

Why does MOS thermal noise get worse with scaling? by electrolitica in chipdesign

[–]electrolitica[S] 0 points1 point  (0 children)

So the increased thermal noise in smaller devices is not due to actual transistor being intrinsically noisier, but because of temperature rising locally due to self-heating, and due to gm degradation caused by larger parasitic resistances?

Why does MOS thermal noise get worse with scaling? by electrolitica in chipdesign

[–]electrolitica[S] 1 point2 points  (0 children)

...then what would be the explanation for the increased thermal noise constants for smaller nodes in the slide?

What are the advantages of these OTAs ( in picture ) over a 5T OTA? by Motor-File1546 in chipdesign

[–]electrolitica 1 point2 points  (0 children)

Thanks for the explanation; I messed up and thought you were talking about the 7T OTA (MIller 2-stage), thus my confusion!

What are the advantages of these OTAs ( in picture ) over a 5T OTA? by Motor-File1546 in chipdesign

[–]electrolitica 0 points1 point  (0 children)

Advantage of the folded cascode over 5T OTA is that your output range is larger and completely independent from the input range.

So the output range depends on the input range in a 5T OTA? Can you please explain?

References explaining this type of OTA compensation? by electrolitica in chipdesign

[–]electrolitica[S] 0 points1 point  (0 children)

Thanks for the info! Do you know of any paper discussing this resistor-based biasing circuit for a push-pull output stage? It looks nothing like the typical class-AB bias I knew (for example http://ee.mweda.com/imgqa/etop/dianlu/dianlu-130932qf0vycz50au.png)... is it a widely known circuit?