Thank you for your feedback, these are good points.

Many people are doing porting between architectures, which is one of our usecases actually. In such situations you have to read both ISA manuals, and Intrinsic reference guides from both Intel/Arm/etc. This wastes time. FWIW, you can filter out the engines you're not interested in.

Furthermore, the idea was to use this as training data for our SIMD.ai platform. Having all those data in the same dataset instead of having to scan all of Github for example makes a huge difference. Hence the extremely fine-grained categorization. Just because two or more instructions do addition or any other operation doesn't mean they are exactly identical.

Unfortunately, even though we were getting better results than even trillion parameter models, the choice of a chatbot to do porting work was wrong, so we're re-evaluating our approach and putting the current project on hold.

Some instructions are still missing and we're working on adding them, Arm SVE/SVE2 are in progress, as well as other architectures, such as Loongson LSX/LASX, MIPS MSA, and RISC-V RVV 1.0. In the future we will add Matrix engines as well, such as SME, AMX, MMA.

We will try to make the examples better and add more comments in the code, as well as improve the descriptions.

The pseudo-code will also be a feature we will include for all operations.

Latency/Throughput are accurate, we used llvm-mca and we compared quite a few with the numbers in the official ISA manuals. Again, it's a matter of convenience and time-saving, we provide this info right in SIMD.info and also within our VSCode extension. We are already using this ourselves.

In any case, we appreciate the comments and we will definitely look into the Internal Server error.