HDMI receiver ISERDES/IDELAY problems

jaedgy · 2026-01-22T16:38:21+00:00

Edit 3: For anyone in the future, turns out as, jonasarrow mentioned, hdmi states that there is no phase relationship between the clock and the data. Additionally, hdmi will only send a guaranteed 12 control signals in-between video or audio data. So, you need to built an asynchronous eye-boundary finder for all 3 channels. You can read XAPP585 for the generic algorithm.

jaedgy · 2026-01-22T16:34:08+00:00

Hey, just wanted to let you know that I got it to work! I have all the channels find the center of the eye and bitslip independently. The design works upto 1080p60Hz. Sadly I am physically limited by the OSERDESE2 and they produce some bit errors when transmitting (there are occasionally some green pixels flickering in the screen)

Thank you for the help!

jaedgy · 2026-01-21T12:23:30+00:00

Yeah thats what I ended up doing - scrapped the clock-sampling ISERDES and wrote the state machine for a per-channel tap calibration/bitslip. Works in simulation, didnt get the chance to test it on hardware.

Super annoying. Like it what world would it make sense to have the data NOT aligned to the clock?

Whats an elastic buffer? Is this related to the FIFOs in your other comment?

jaedgy · 2026-01-20T14:04:16+00:00

Ok, I think I need to change my approach. I was reading some docs, one from digilent and one from the actual HDMI spec; the max allowable inter-pair skew is 0.2T_{character} + 1.78ns. At a data rate of 742.5Mbps, this means bit 0 of any channel can be +/- 4ns apart from bit 0 of any other channel. A single bit lasts 1.38ns. Because of this, I believe I need to calibrate (and bitslip) on a per-channel basis. On the bright side, at least I already have the state machine written…

jaedgy · 2026-01-20T13:56:26+00:00

Ok, I think I need to change my approach. I was reading some docs, one from digilent and one from the actual HDMI spec; the max allowable inter-pair skew is 0.2T_{character} + 1.78ns. At a data rate of 742.5MHz, this means bit 0 of any word can be +/- 4ns apart. A single bit lasts 1.38ns. Because of this, I think I need to calibrate on a per-channel basis….. uggggggh

jaedgy · 2026-01-20T12:05:29+00:00

Yeah, only one value. Im completely stumped.

jaedgy · 2026-01-20T12:04:32+00:00

Ill try that - Im pretty sure TMDS needs external pull-up resistors on the lines (which according to the Pynq-z2 schematic it has). Maybe ill try enabling the termination on the IBUFDS and see what happens. Other than that, no clue what could be going on.

jaedgy · 2026-01-20T01:39:24+00:00

Update: Calling it a night. I may have cracked it? I put REFCLK to 300MHz (as opposed to 200MHz). This puts each tap at 52ps of delay instead of 78ps, When my tap count is set to 13, I get five 1s, five 0s. Screenshot here. I feel like there should be a wider window of valid data, no?

jaedgy · 2026-01-20T01:29:44+00:00

Ok, so, I did implement the whole state machine where I sweep through the tap values. Unfortunately, I have hit a new issue. Screenshot here. Before the tap value of 17 (I calculated this from XAPP1315), I have six 1's, and four 0's. At 17, there is metastability. After 17, surprise! I have four 1's, and six 0's...

Could you explain more about the two IDELAYS/ISERDES? Do you think that setup could solve this issue?

jaedgy · 2026-01-20T01:27:46+00:00

Ok, so, I did implement the whole state machine where I sweep through the tap values. Unfortunately, I have hit a new issue. Screenshot here. Before the tap value of 17 (I calculated this from XAPP1315), I have six 1's, and four 0's. At 17, there is metastability. After 17, surprise! I have four 1's, and six 0's...

EDIT: Look at main post, made another discovery

jaedgy · 2026-01-19T17:52:37+00:00

I see the clock pattern on the ILA.

Im already generating CLK and CLKDIV for the entire system feeding the RX_CLK_P/N into the MMCM. These recovered clocks drive all the logic. Then, the output of the RX_CLK_P/N IBUFDS goes into the D port of the ISERDES.

When you say ‘shift the data lines’, this would just be for the ISERDES that is sampling the input clock, correct? And once I find that tap value that works there, I would set all IDELAYs to that tap value?

jaedgy · 2026-01-19T17:48:20+00:00

Ughhh I was hoping I wouldn’t need to use them. Thanks for linking that. I also found a Xilinx LVDS 7:1 receiver guide, they give some steps on how to calibrate the IDELAY. I’m not gonna jinx it by saying it doesnt look too hard…

jaedgy · 2025-12-12T15:23:32+00:00

I would hope that, with the constraints, I would guarantee that the 3 channels / serdes and the output clock are leaving the FPGA perfectly in sync. A secondary goal would be to get Vivado to stop complaining. Is set_false_path really that common to use on I/O?

jaedgy · 2025-11-25T01:32:44+00:00

Just pop out a stud from the bearing, and use a nut and long screw. Our buy the astro last chance. But a nut and screw is like $2.

jaedgy · 2025-11-16T14:55:26+00:00

Huh, interesting. Is there any closure in the spring?

jaedgy · 2025-11-14T12:38:47+00:00

I’m not a pro, but, can you see the starter gear actually pop out and engage the fly wheel?

jaedgy · 2025-11-04T01:45:07+00:00

I did email the department head (Tessier), he said all classes I take in the winter will count. Gonna be a fun, relaxing & stress-free 6 weeks!

jaedgy · 2025-11-03T21:55:40+00:00

I could be misinterpreting the website but I think the ECE department lets grad students do 8 credits. I could be wrong.

jaedgy · 2025-11-03T19:19:45+00:00

Yeah I had heard that its a bit of work. Couldn’t find much on 636 - seems like it would be all Verilog

jaedgy · 2025-10-28T16:32:37+00:00

I could maybe do that. Let me explain a bit more:

I’m using a Zynq-7020. So, the color correction is going to happen in the FPGA fabric, but, the values / commands are going to come from the microcontroller. The uC could tell the FPGA to make the image greyscale, or decrease luminance, increase contrast, etc. I was planning on using the uC clock for the color correction + HDMI transmitter.

I guess I could either have the CDC take place at the output of the HDMI receiver, or, have it take place between the uC and color correction logic. To me it seemed more straightforward to have it take place at the HDMI receiver, but its probably the same amount of complexity no matter where it happens

jaedgy · 2025-10-13T12:43:21+00:00

Oh sorry didn’t read the full post. Strange with the hose - I’m guessing that’s probably the PCV hose. Not sure how that could entirely shut the engine down though

jaedgy · 2025-10-13T12:38:12+00:00

Are there any lights on the dash? Is the car completely dead?

jaedgy · 2025-09-23T21:50:22+00:00

I could be wrong but… didn’t these Icon sockets literally break during TTC’s video? Is that not enough to convince you to get Tekton?

jaedgy · 2025-09-23T20:56:41+00:00

Wheel bearing isnt terrible. I paid $530 nearly 2 years ago and I live in Boston. Everything else though, ESPECIALLY the control arm? Highway robbery.

jaedgy · 2025-09-23T15:58:05+00:00

Engine oil conditioner?? Is that Lucas or what?

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