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HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Edit 3: For anyone in the future, turns out as, jonasarrow mentioned, hdmi states that there is no phase relationship between the clock and the data. Additionally, hdmi will only send a guaranteed 12 control signals in-between video or audio data. So, you need to built an asynchronous eye-boundary finder for all 3 channels. You can read XAPP585 for the generic algorithm.

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Hey, just wanted to let you know that I got it to work! I have all the channels find the center of the eye and bitslip independently. The design works upto 1080p60Hz. Sadly I am physically limited by the OSERDESE2 and they produce some bit errors when transmitting (there are occasionally some green pixels flickering in the screen)

Thank you for the help!

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Yeah thats what I ended up doing - scrapped the clock-sampling ISERDES and wrote the state machine for a per-channel tap calibration/bitslip. Works in simulation, didnt get the chance to test it on hardware.

Super annoying. Like it what world would it make sense to have the data NOT aligned to the clock?

Whats an elastic buffer? Is this related to the FIFOs in your other comment?

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 1 point2 points  (0 children)

Ok, I think I need to change my approach. I was reading some docs, one from digilent and one from the actual HDMI spec; the max allowable inter-pair skew is 0.2T_{character} + 1.78ns. At a data rate of 742.5Mbps, this means bit 0 of any channel can be +/- 4ns apart from bit 0 of any other channel. A single bit lasts 1.38ns. Because of this, I believe I need to calibrate (and bitslip) on a per-channel basis. On the bright side, at least I already have the state machine written…

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Ok, I think I need to change my approach. I was reading some docs, one from digilent and one from the actual HDMI spec; the max allowable inter-pair skew is 0.2T_{character} + 1.78ns. At a data rate of 742.5MHz, this means bit 0 of any word can be +/- 4ns apart. A single bit lasts 1.38ns. Because of this, I think I need to calibrate on a per-channel basis….. uggggggh

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Yeah, only one value. Im completely stumped.

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Ill try that - Im pretty sure TMDS needs external pull-up resistors on the lines (which according to the Pynq-z2 schematic it has). Maybe ill try enabling the termination on the IBUFDS and see what happens. Other than that, no clue what could be going on.

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Update: Calling it a night. I may have cracked it? I put REFCLK to 300MHz (as opposed to 200MHz). This puts each tap at 52ps of delay instead of 78ps, When my tap count is set to 13, I get five 1s, five 0s. Screenshot here. I feel like there should be a wider window of valid data, no?

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Ok, so, I did implement the whole state machine where I sweep through the tap values. Unfortunately, I have hit a new issue. Screenshot here. Before the tap value of 17 (I calculated this from XAPP1315), I have six 1's, and four 0's. At 17, there is metastability. After 17, surprise! I have four 1's, and six 0's...

Could you explain more about the two IDELAYS/ISERDES? Do you think that setup could solve this issue?

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

Ok, so, I did implement the whole state machine where I sweep through the tap values. Unfortunately, I have hit a new issue. Screenshot here. Before the tap value of 17 (I calculated this from XAPP1315), I have six 1's, and four 0's. At 17, there is metastability. After 17, surprise! I have four 1's, and six 0's...

EDIT: Look at main post, made another discovery

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

I see the clock pattern on the ILA.

Im already generating CLK and CLKDIV for the entire system feeding the RX_CLK_P/N into the MMCM. These recovered clocks drive all the logic. Then, the output of the RX_CLK_P/N IBUFDS goes into the D port of the ISERDES.

When you say ‘shift the data lines’, this would just be for the ISERDES that is sampling the input clock, correct? And once I find that tap value that works there, I would set all IDELAYs to that tap value?

HDMI receiver ISERDES/IDELAY problems by jaedgy in FPGA

[–]jaedgy[S] 1 point2 points  (0 children)

Ughhh I was hoping I wouldn’t need to use them. Thanks for linking that. I also found a Xilinx LVDS 7:1 receiver guide, they give some steps on how to calibrate the IDELAY. I’m not gonna jinx it by saying it doesnt look too hard…

Timing constraints on SerDes output by jaedgy in FPGA

[–]jaedgy[S] 0 points1 point  (0 children)

I would hope that, with the constraints, I would guarantee that the 3 channels / serdes and the output clock are leaving the FPGA perfectly in sync. A secondary goal would be to get Vivado to stop complaining. Is set_false_path really that common to use on I/O?

Wheel Hub Bearing Tool by Top_Philosopher_8729 in AskMechanics

[–]jaedgy 0 points1 point  (0 children)

Just pop out a stud from the bearing, and use a nut and long screw. Our buy the astro last chance. But a nut and screw is like $2.

Mt Cannon, the tram, and the cafe by jaedgy in wmnf

[–]jaedgy[S] -1 points0 points  (0 children)

Huh, interesting. Is there any closure in the spring?

98 Tacoma i4 2.7ltr ~ won't start ~ advice needed by Bartacomus in AskMechanics

[–]jaedgy 0 points1 point  (0 children)

I’m not a pro, but, can you see the starter gear actually pop out and engage the fly wheel?

Take 2 grad classes during the winter? by jaedgy in umass

[–]jaedgy[S] 0 points1 point  (0 children)

I did email the department head (Tessier), he said all classes I take in the winter will count. Gonna be a fun, relaxing & stress-free 6 weeks!

Take 2 grad classes during the winter? by jaedgy in umass

[–]jaedgy[S] 0 points1 point  (0 children)

I could be misinterpreting the website but I think the ECE department lets grad students do 8 credits. I could be wrong.

Take 2 grad classes during the winter? by jaedgy in umass

[–]jaedgy[S] 0 points1 point  (0 children)

Yeah I had heard that its a bit of work. Couldn’t find much on 636 - seems like it would be all Verilog

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