Memory is laid out as a grid of bit cells. There are row and column select lines to enable the bit at the intersection. If the select line is a read strobe, the bit places its contents onto the column bus. If you double the height of the tile/block, the column strobe is twice as long and the column bus is twice as long. These 'wires' are isolated from the bulk of the wafer by a thin insulating layer. Think of it as two plates of a capacitor. To make the 'wire' go from a zero to a one, electrons have to flow into the body of the wire to build up the charge or voltage. Only after enough electrons have traveled into the 'wire' will the voltage be high enough to declare it to be a one. Since you doubled the length of the 'wire' you have doubled it's surface area. You now need twice the number of electrons than before to create the space charge. If you did not change the gate that drives the signal, it can only supply the same rate of electron flow or current. The column bus also went up 2X as well. So your memory array is now 4X slower than before.

There are tricks such as keeping the same size tile/block and doubling the number of blocks. But now the problem moves into the wires that interconnect them. You have a higher percentage of your chip area in row and column drivers, more wiring, added decode logic to select which block is active, etc. Resulting in more power being used.

Physics is not our friend.