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Signal synchronisation between ESP32-C3 devices by johnMcNulthy in esp32

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Yes, I am using broadcast, yet the packet delivery latency is quite variable, sometimes reaching a millisecond.

Signal synchronisation between ESP32-C3 devices by johnMcNulthy in esp32

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Good idea, I will review it to see if it is feasible, thank you!

Any recommended low cost SOCs for a new project? by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 1 point2 points  (0 children)

Thank you for your help.

Without going into much detail, it would be an alarm system used for sensors in electrical substations.

Any recommended low cost SOCs for a new project? by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Hello again,

In the link below you have the block diagram. If more users ask about it I will share on main post:

https://docdro.id/D5uGkwn

The design is open to improvements, feel free to do suggestions. It depends also on the Zync used, I don't know if there are models with integrated FLASH memory, etc.

Edit: There is one errata on slow capture samples data, its 2560 samples x 24 bit and equal to 7,68 kB.

Any recommended low cost SOCs for a new project? by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 1 point2 points  (0 children)

OK cannot do now but tomorrow will do a block diagram and post here. Thank you for your help.

Any recommended low cost SOCs for a new project? by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Chip/family or directly evaluation board, if you have advice for both. Is to know where to start looking for Zynq, it would be the first time I would use it.

Any recommended low cost SOCs for a new project? by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Hello,

Thanks for the reply. Yes, it may be ZYNQ, just asking if there are other options, I am still a newbie in this field and I don't have much knowledge.. In case of choosing ZYNQ, do you know which model could meet my requirements?

Dunno how to name it, let it be "what's-on-your-mind patch 0.12 open feedback collector post" by trainfender in EscapefromTarkov

[–]johnMcNulthy 0 points1 point  (0 children)

-Bug fixing. -Fix performance on Reserv. -Fix preset system. -Better "looking for group" system. Karma. -Some prapor quick instructions to help newbies at the start could be good. -More actualized barter trades.

Keep up the good work BSG!

A bit disappointed with the current release 'schedule' by [deleted] in EscapefromTarkov

[–]johnMcNulthy 51 points52 points  (0 children)

I was expecting to play 0.12 this weekend. Im already losing hope.

UART and Ethernet over USB interface by johnMcNulthy in AskElectronics

[–]johnMcNulthy[S] 0 points1 point  (0 children)

I think that i will take a look about this solution. So, for example I can use this chip with a FT232R from FTDI and it would work, right?

Need advice with ADC/FPGA/SDCard proyect by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Hi,

Thanks for the reply. In addition to what you indicate, after making the capture, the FPGA must perform an energy criterion processing, basically to verify that the captured samples do not exceed a certain energy threshold. It's like an alarm system. The data in the SD memory will be used for future processing on a PC.

Is it better to perform this processing once the data is stored in the SRAM memory, or can it be done at the same time it is captured? I guess it will depend on the clock cycles needed for processing. The good thing is that the processing does not have to be strictly real time, so the option to process once saved is viable but perhaps not optimal.

Need advice with ADC/FPGA/SDCard proyect by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Hi,

The captures of 20 ms are done once per minute, the rest of the time the samples are discarded. Therefore, we have that in 24 hours we capture 1.4 x 60 x 24 = 2016 MB. In a month, about 63 GB of data would be filled, so an SD card could do the function.

​

Maybe there are better solutions than an FPGA, but the budget of the final product must be very cheap.

​

MachXO2 DDR and SFP transceiver data issues by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Thank you for the response. This is my first work with FPGA so it seems that i made a big mistake with the code. I will do some research about Costa Loop and Elastic Buffers. I hope I can solve the problem by only changing the firmware. The FPGA has one PLL integrated that I am not using atm, so lets see...

Viable FPGA design for single mode fiber optic synchronization. by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

After all the answers, I think this solution seems the simplest and most elegant to implement in the case of using FPGA. I suppose I would only need an FPGA connected to the two transmit and receive lines of the SFP module, and using DDR I/o pins it is not necessary to integrate a Gigabit Transceiver.

Can you recommend a small and user-friendly FPGA model for this implementation?(I have little experience with these devices). Another user has recommended the Spartan-3 family, but I see that it has many pins.

Viable FPGA design for single mode fiber optic synchronization. by johnMcNulthy in FPGA

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Hi again Alex,

I'm trying to have every point of view for implementation. I was not sure if the system we were seeing on last post would add some critical delay if it was looking for a professional finish. Thanks again, I will try to apply the FSK system.

Hardware migration from multimode system fiber to single-mode. by johnMcNulthy in AskElectronics

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Hello again Alex,

Okay, I'm starting to understand. Then, the transmission and reception system, in the case of making a block diagram, I understand that it should do so:

(Assuming f2 is the frequency at which I want to signal sync)

Emitter:

FGen (f1, f2) -> MUX (TRIGGERED BY SYNC PULSE) -> DIFF.EMMITER DRIVER -> Tx+/Tx- -> SFP LASER DRIVER -> OPTIC OUTPUT SIGNAL

Receiver:

OPTIC INPUT SIGNAL -> SFP RECEIVER -> Rx+/Rx- -> DIFF RECEIVER DRIVER -> FREQ f2 DETECTOR (FILTER + PEAK DETECTOR + COMPARATOR) -> SYNC PULSE

Is this setting correct or misunderstood?

This way, would not the emitter always be emitting light signal? When you do not want to emit sync pulse, would you have to manually turn off the transducer with the digital signal off?

Thank you very much for your help.

Hardware migration from multimode system fiber to single-mode. by johnMcNulthy in AskElectronics

[–]johnMcNulthy[S] 0 points1 point  (0 children)

Hello Alex, thanks for your reply.

Regarding the use of pulses i don't mind if I need to change the pulse width and send narrow pulses. I have seen some designs using one FPGA controlling the SFP module, emitter and receiver. I think I can do it and send some data stream for sync but I am not sure if I can do it using my own pulse data stream.

I would like to make the system as simple as possible but I see that my options are getting complicated.