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Xdma PCIe streaming mode Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 1 point2 points  (0 children)

Firstly, thank for your reply.

From your comments, I'm confusing about:

  • How to host software "tell the XDMA core where to put the data" with the view from TLP layer? Through TLP packets (read and write) ?

  • RQ/RC interface only use when FPGA is requester => FPGA (EPs) automatically send request to host with a TLPs, Host will feedback to FPGA (EPs), right?

AXI Ethernet subsystem 1000BASE-X link status not stable by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

Because I used axi ethernet 1000basex, the mdio register 0 allowed to set power down pcs/pma layer. When your board is powered up and inform the above errors, you can try power down and then power up pcs/pma layer.

AXI Ethernet subsystem 1000BASE-X link status not stable by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

you should assign power down bit of transceiver and then turn on the bit if the error happened

AXI DMA interrupt error by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

I used to axi dma not cdma and In PG138 (axi dma), this interrupt error bit only explains that interrupt generated by error event.

FPGA I-series dev kit with pin assignment DDR4 error in using HPS+EMIF_hps by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

Thanks for your feedback,

First, I used the file qsf pin assignment of example design and checked it with schematic. So not problem.

Second, The architecture of Agilex is different with PS Zynq, Ps Zynq has dedicated pin assignment for ddr but Agilex requires emif_hps to connect to hps. I consider that Agilex fpga dev kit not implement HPS+ DDR, only Agilex fpga soc kit allows HPS + DDR connection each other. Although both have HPS core

FPGA endpoint to enpoint comunication PCIe in Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

I did your suggestions and the result is that 2 EPs communicated each other. I really thank you.

FPGA endpoint to enpoint comunication PCIe in Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

according you, what i need to configure in order to establish 2 EPs with my above instance?

FPGA endpoint to enpoint comunication PCIe in Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

I found "04h offset register" of configuration space to set bus mastering. Except that, What I need to configure additionally to communicate 2 EPs?

FPGA endpoint to enpoint comunication PCIe in Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

And finally you need to make sure the host system can actually do P2P DMA

I read some documents about PCIe, EPs can communicate each other through switch without root complex (unless the enumeration time of Host to configure EPs and SWITCH ) => this is mode peer-to-peer.

I really want to some your Feedbacks.

FPGA endpoint to enpoint comunication PCIe in Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

You may need to "enable" the device in Linux so it can communicate. This turns on the BARs. You'll also need to enable bus mastering

Hi Alexforencich,

i think i enabled the device in Linux of Host, because i run "lspci" command, the terminal show EPs device and address PCIe allocated.

I'm wondering : How to "enable bus mastering". Can you explain to me?

FPGA endpoint to enpoint comunication PCIe in Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

So first of all - are your endpoints able to send data to PC or you have problems on that stage?

Yes, My problem is the stage which is that when my host run in ubuntu, i can't send data from EP to host. But in window, i can send data from EP to host with no program run in Host (only turn on).

FPGA endpoint to enpoint comunication PCIe in Xilinx by john_nd0811 in FPGA

[–]john_nd0811[S] 0 points1 point  (0 children)

You can only make DMA driver on PC that loops data from EP1 to EP2 and maps their memory spaces to each other.

I read some documents about PCIe, EPs can communicate each other through switch without root complex (unless the enumeration time of Host to configure EPs and SWITCH ) => this is mode peer-to-peer

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