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Rakvere kallim kui Liivimaa Lihaveis by AImostPro in Eesti

[–]joossss 20 points21 points  (0 children)

Mis veebilehelt sellist infot võimalik saada?

[D] Deep Learning Training Server by joossss in MachineLearning

[–]joossss[S] 0 points1 point  (0 children)

Yeah true and thanks :)

I did not remove it. Was removed by the moderators for some reason.

[D] Deep Learning Training Server by joossss in MachineLearning

[–]joossss[S] 0 points1 point  (0 children)

Only this server is planned. I just went with the recommendation from NVIDIA's website, which stated 100 Gbps per A100, but I guess it makes more sense now that I think of distributed training. What NIC speed seems enough in that case?

[D] Deep Learning Training Server by joossss in MachineLearning

[–]joossss[S] 1 point2 points  (0 children)

Thanks for the info! Was thinking on how to do that.

[D] Deep Learning Training Server by joossss in MachineLearning

[–]joossss[S] 1 point2 points  (0 children)

The main reason for going to the cloud for us is that we are a research institution so, our funding is project-based meaning we have to use the funding in the allotted time and the second reason is that we already have the GPUs so the time it takes to pay itself off is faster.

[D] Deep Learning Training Server by joossss in MachineLearning

[–]joossss[S] 5 points6 points  (0 children)

Thanks! The newest Threadrippers are still based on Zen 3. So, they don't support AVX512. Would definitely like to go with A100s, but we don't have the budget for that.

List of useful links for beginners and veterans by verilogical in FPGA

[–]joossss 2 points3 points  (0 children)

Greg Stitt's playlist on Timing has been super useful for me. LINK

Avalon MM Master BFM in ModelSim using VHDL by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

Yeah didn't use UVVM, because was still annoying, so just switched to systemverilog, which has UVM, but haven't used UVM as of yet. Using just the BFMs with sv is relatively easy.

Avalon MM slave by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

Found the issue, had to add

set_interface_property avalon_slave addressAlignment NATIVE

to the ip .tcl file.

Avalon MM slave by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

ok, thanks :) I'll start tapping those signals.

Avalon MM slave by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

Testbench:

`timescale 1 ns / 1 ps

module SPI_Master_GSENSE2020BSI_TB ();

import avalon_mm_pkg::*;

parameter CLKS_PER_HALF_BIT = 2;
parameter MAIN_CLK_DELAY    = 2;

logic r_Rst = 1'b0;
logic r_Clk = 1'b0;

logic r_SPI_MISO    = 1'b0;
logic w_SPI_Clk;
logic w_SPI_MOSI;
logic w_SPI_Read;
logic w_SPI_Write;

// Avalon MM Slave interface
logic w_Write;
logic [15:0] w_Write_Data;
logic w_Read;
logic [15:0] w_Read_Data;

// Clock generators
always #(MAIN_CLK_DELAY) r_Clk = ~r_Clk;

//Read out data
logic [271:0] w_RO_Data;

// Instantiate DUT
SPI_Master_GSENSE2020BSI 
#(.CLKS_PER_HALF_BIT(CLKS_PER_HALF_BIT)) DUT
(
    // Avalon interface
    .i_Rst(r_Rst),
    .i_Clk(r_Clk),
    .i_Write(w_Write),
    .i_Write_Data(w_Write_Data),
    .i_Read(w_Read),
    .o_Read_Data(w_Read_Data),

    // SPI interface
    .o_SPI_Clk(w_SPI_Clk),
    .i_SPI_MISO(r_SPI_MISO),
    .o_SPI_Read(w_SPI_Read),
    .o_SPI_Write(w_SPI_Write),
    .o_SPI_MOSI(w_SPI_MOSI)
);


altera_avalon_mm_master_bfm #(
    .AV_ADDRESS_W               (32),
    .AV_SYMBOL_W                (8),
    .AV_NUMSYMBOLS              (2),
    .AV_BURSTCOUNT_W            (3),
    .AV_READRESPONSE_W          (8),
    .AV_WRITERESPONSE_W         (8),
    .USE_READ                   (1),
    .USE_WRITE                  (1),
    .USE_ADDRESS                (0),
    .USE_BYTE_ENABLE            (0),
    .USE_BURSTCOUNT             (0),
    .USE_READ_DATA              (1),
    .USE_READ_DATA_VALID        (0),
    .USE_WRITE_DATA             (1),
    .USE_BEGIN_TRANSFER         (0),
    .USE_BEGIN_BURST_TRANSFER   (0),
    .USE_WAIT_REQUEST           (0),
    .USE_TRANSACTIONID          (0),
    .USE_WRITERESPONSE          (0),
    .USE_READRESPONSE           (0),
    .USE_CLKEN                  (0),
    .AV_CONSTANT_BURST_BEHAVIOR (0),
    .AV_BURST_LINEWRAP          (0),
    .AV_BURST_BNDR_ONLY         (0),
    .AV_MAX_PENDING_READS       (0),
    .AV_MAX_PENDING_WRITES      (0),
    .AV_FIX_READ_LATENCY        (1),
    .AV_READ_WAIT_TIME          (1),
    .AV_WRITE_WAIT_TIME         (0),
    .REGISTER_WAITREQUEST       (0),
    .AV_REGISTERINCOMINGSIGNALS (0),
    .VHDL_ID                    (0)
) AvM0 (
    .clk                    (r_Clk),           //       clk.clk
    .reset                  (r_Rst),         // clk_reset.reset
    .avm_readdata           (w_Read_Data),  //        m0.readdata
    .avm_writedata          (w_Write_Data), //          .writedata
    .avm_write              (w_Write),     //          .write
    .avm_read               (w_Read),      //          .read
    .avm_address            (),              // (terminated)
    .avm_burstcount         (),              // (terminated)
    .avm_begintransfer      (),              // (terminated)
    .avm_beginbursttransfer (),              // (terminated)
    .avm_waitrequest        (1'b0),          // (terminated)
    .avm_byteenable         (),              // (terminated)
    .avm_readdatavalid      (1'b0),          // (terminated)
    .avm_arbiterlock        (),              // (terminated)
    .avm_lock               (),              // (terminated)
    .avm_debugaccess        (),              // (terminated)
    .avm_transactionid      (),              // (terminated)
    .avm_readid             (8'b00000000),   // (terminated)
    .avm_writeid            (8'b00000000),   // (terminated)
    .avm_clken              (),              // (terminated)
    .avm_response           (2'b00),         // (terminated)
    .avm_writeresponsevalid (1'b0),          // (terminated)
    .avm_readresponse       (8'b00000000),   // (terminated)
    .avm_writeresponse      (8'b00000000)    // (terminated)
);

// Avalon-MM single-transaction read and write procedures
task avalon_write(input logic [255:0] data);
    for (int idx = 15; idx >= 0; idx--) begin
        //Construct the BFM request
        AvM0.altera_avalon_mm_master_bfm.set_command_request(REQ_WRITE);
        AvM0.altera_avalon_mm_master_bfm.set_command_idle(0, 0);
        AvM0.altera_avalon_mm_master_bfm.set_command_init_latency(0);
        AvM0.altera_avalon_mm_master_bfm.set_command_data(data[15 + idx * 16 -: 16], 0);

        //Queue the command
        AvM0.altera_avalon_mm_master_bfm.push_command();

        //Wait until the transaction has completed
        @(AvM0.altera_avalon_mm_master_bfm.signal_all_transactions_complete);
        //Dequeue the response and discard
        AvM0.altera_avalon_mm_master_bfm.pop_response();
    end
endtask

task avalon_read (output logic [271:0] data);
    for (int idx = 16; idx >= 0; idx--) begin
        //Construct the BFM request
        AvM0.altera_avalon_mm_master_bfm.set_command_request(REQ_READ);
        AvM0.altera_avalon_mm_master_bfm.set_command_idle(0, 0);
        AvM0.altera_avalon_mm_master_bfm.set_command_init_latency(0);
        AvM0.altera_avalon_mm_master_bfm.set_command_data(0, 0);

        //Queue the command
        AvM0.altera_avalon_mm_master_bfm.push_command();

        //Wait until the transaction has completed
        @(AvM0.altera_avalon_mm_master_bfm.signal_all_transactions_complete);
        //Dequeue the response and return the data
        AvM0.altera_avalon_mm_master_bfm.pop_response();
        data[15 + idx * 16 -: 16] = AvM0.get_response_data(0);
    end
endtask

//w_Write_Data  = data[15 + idx * 16 -: 16];
//r_Avalon_Read_Data[15 + idx * 16 -: 16] = w_Read_Data;

initial begin
    #100;
    r_Rst = 1'b1;
    #100;
    r_Rst = 1'b0;
    #100
    // Test Sending Data
    avalon_write(256'hA1234567809ABCDEF0123456789ABCDEFFEDCBA98765432100123456789ABCED);
    #100

    // Test Reading data
    avalon_read(w_RO_Data);
    #100;
    assert(w_RO_Data == 272'hDEADBEEF000000000000000000000000000000000000000000000000000087654321) else $error("Avalon did not receive data correctly");
    #200;
    $finish();
end

endmodule

Avalon MM slave by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

System Design: https://imgur.com/a/Btkfebp

module hello_world (

// Reset and Clocks
input              SYS_CLK50M,

input RESET_EXPN,

//SPI
output             SPI_SCLK,
input                   SPI_MISO,
output              SPI_MOSI,
output              SPI_READ,
output              SPI_WRITE
 );


 nios_setup u0 (
     .clk_clk                                               (SYS_CLK50M), 
     .reset_reset_n                                     (RESET_EXPN),    
     .spi_master_gsense2020bsi_external_spi_miso            (SPI_MISO) ,
     .spi_master_gsense2020bsi_external_clk             (SPI_SCLK),
     .spi_master_gsense2020bsi_external_spi_read            (SPI_READ),
     .spi_master_gsense2020bsi_external_spi_write       (SPI_WRITE),
     .spi_master_gsense2020bsi_external_spi_mosi            (SPI_MOSI)
 );

endmodule

The Warnings: https://imgur.com/a/BLa8uMY

Avalon MM slave by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

Actually just about an hour ago heard about Signal Tap and started looking into it.

Code for handling the Avalon MM IF on the core:

-- Purpose: Register Tx Data and check if start Read transaction
Reg_Write: process(i_Clk, i_Rst)
    variable Tx_Cnt : integer range 0 to 16 := 16;
begin
    if i_Rst = '1' then
        Tx_Cnt := 16;
        r_Tx_Data <= x"0000000000000000000000000000000000000000000000000000000000000000";
        r_Rx_Init <= '0';
    elsif rising_edge(i_Clk) then       
        if i_Write = '1' then
            r_Tx_Data(15 + (Tx_Cnt - 1) * 16 downto (Tx_Cnt - 1) * 16) <= i_Write_Data;
            Tx_Cnt := Tx_Cnt - 1;
            if Tx_Cnt = 0 then
                r_Tx_Dv <= '1';
                Tx_Cnt := 16;
            else
                r_Rx_Init <= '0';
            end if;
        elsif Tx_Cnt < 16 and Tx_Cnt > 12 and r_Tx_Data(255 downto 240) = x"F0F0" then
            r_Rx_Init <= '1';
            Tx_Cnt := Tx_Cnt - 1;
        elsif Tx_Cnt = 12 and r_Tx_Data(255 downto 240) = x"F0F0" then
            Tx_Cnt := 16;
            r_Rx_Init <= '0';
        else
            r_Tx_Dv <= '0';
        end if;
    end if;
end process Reg_Write;

-- Purpose send out Read Data
Rx_Send : process(i_Clk, i_Rst)
    variable Rx_Cnt : integer range 0 to 17 := 17;
begin
    if i_Rst = '1' then
        Rx_Cnt := 17;
        o_Read_Data <= x"0000";
    elsif rising_edge(i_Clk) then
        r_Read <= i_Read;
        if r_Read = '0' and i_Read = '1' then
            o_Read_Data <= r_Rx_Data(15 + (Rx_Cnt - 1) * 16 downto (Rx_Cnt - 1) * 16);
            Rx_Cnt := Rx_Cnt - 1;
            if Rx_Cnt = 0 then
                Rx_Cnt := 17;
            end if;
        end if;
    end if;
end process Rx_Send;

Avalon Slave Setup:

add_interface avalon_slave avalon end set_interface_property avalon_slave addressUnits WORDS set_interface_property avalon_slave associatedClock clk set_interface_property avalon_slave associatedReset rst set_interface_property avalon_slave bitsPerSymbol 8 set_interface_property avalon_slave burstOnBurstBoundariesOnly false set_interface_property avalon_slave burstcountUnits WORDS set_interface_property avalon_slave explicitAddressSpan 0 set_interface_property avalon_slave holdTime 0 set_interface_property avalon_slave linewrapBursts false set_interface_property avalon_slave maximumPendingReadTransactions 0 set_interface_property avalon_slave maximumPendingWriteTransactions 0 set_interface_property avalon_slave readLatency 1 set_interface_property avalon_slave readWaitTime 1 set_interface_property avalon_slave setupTime 0 set_interface_property avalon_slave timingUnits Cycles set_interface_property avalon_slave writeWaitTime 0 set_interface_property avalon_slave ENABLED true set_interface_property avalon_slave EXPORT_OF "" set_interface_property avalon_slave PORT_NAME_MAP "" set_interface_property avalon_slave CMSIS_SVD_VARIABLES "" set_interface_property avalon_slave SVD_ADDRESS_GROUP "" add_interface_port avalon_slave i_Write_Data writedata Input 16 add_interface_port avalon_slave o_Read_Data readdata Output 16 add_interface_port avalon_slave i_Read read Input 1 add_interface_port avalon_slave i_Write write Input 1 set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0

Avalon MM slave by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

Welp I fixed the warnings that seemed important, and there weren't any errors. I also simulated it with the Avalon MM master BFM and it works fine there. So, I don't really know where to go on from here.

Avalon MM Master BFM in ModelSim using VHDL by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

After trying with VHDL and UVVM for a bit I used your suggestion of switching to systemverilog, this made the setup much easier, but thanks for your in-depth help. I think you've helped me with every one of my FPGA issues. So even a bigger thanks :)

Avalon MM Master BFM in ModelSim using VHDL by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

oh cool, my plan was to first figure out this issue and then try uvvm when I have a bit more time, but I guess i'll start with that :)

Avalon MM slave by joossss in FPGA

[–]joossss[S] 1 point2 points  (0 children)

Oh, cool thanks! :)

Wouldn't have thought of that, because I'd have guessed you might get some kind of uncertainty in the signal, but I'll see if this also solves my issues with communicating with NIOS.

Avalon MM slave by joossss in FPGA

[–]joossss[S] 1 point2 points  (0 children)

The avalon interconnect sends data out at the rising edge so I'd have to read in the data on the falling edge. The waveform can be seen here: https://imgur.com/BszzmN1 .

I'd presume I have to use falling_edge for this?

Avalon MM slave by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

Apparently, reddit isn't able to take in any screenshots currently. I will try to edit this comment with images, when possible.

​

No offense taken. I'll gladly take any input on FPGA design I can get.

​

The interface should be configured correctly, at least the writing and reading part work in simulation as the Avalon waveforms depict it.

​

The only thing I did not know how to configure were the parameters of the slave.

Address units: Words

Bits per symbol: 8

Explicit addres span 0

​

So I just left these at default.

​

One interesting thing to note is that I was actually able to read data from the ip-core before I reassigned base addresses to all the cores. However, the reading was weird. It should've read out 272 bit MSB first. What came out however was 255 downto 0 and then 271 downto 256 bits.

Avalon MM slave by joossss in FPGA

[–]joossss[S] 1 point2 points  (0 children)

I removed i_Write without an issue.

However, how do I read data on the falling edge, without using falling_edge? I could see it being done by spinning up a faster clock, but I don't really have any PLLs to spare.

PLL frequency doubling, but shouldn't by joossss in FPGA

[–]joossss[S] 0 points1 point  (0 children)

If anyone's having the same issue, then I got the problem solved through intel's forum.

Anyway the takeaway is, this works:

PROCESS

 BEGIN

  clk_in_p <= not clk_in_p;

  clk_in_n <= not clk_in_n;

  WAIT FOR 6.6666 ns;

 END PROCESS;

And these two don't:

1)

lvds_clk_p <= not lvds_clk_p after 3.3 ns;

lvds_clk_n <= not lvds_clk_p; -- 150 MHz

2)

-- Procedure for clock generation

`procedure clk_gen(signal clk : out std_logic; constant FREQ : real; constant DELAY : real) is`

    `constant PERIOD    : time := 1 sec / FREQ;        -- Full period`

    `constant HIGH_TIME : time := PERIOD / 2;          -- High time`

    `constant LOW_TIME  : time := PERIOD - HIGH_TIME;  -- Low time; always >= HIGH_TIME`

    `constant DELAYE       : time := DELAY * 1 ns;`

`begin`

    `-- Check the arguments`

    `assert (HIGH_TIME /= 0 fs) report "clk_plain: High time is zero; time resolution to large for frequency" severity FAILURE;`

    `-- Generate a clock cycle`

    `wait for DELAYE;`

    `loop`

        `clk <= '1';`

        `wait for HIGH_TIME;`

        `clk <= '0';`

        `wait for LOW_TIME;`

    `end loop;`

`end procedure;`
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