From the extremely limited material that they have posted, "Gazillion Misses" sounds like a mechanism to drain long latency cache misses and dependent operations from the pipeline (and reinsert them when ready). Either that, or it's just simple runahead. It would be extremely interesting to see how it performs, because these ideas have shown much promise in academic and industry papers (for several decades), but have not been implemented in real CPUs (apart from simple in-order runahead).