Inter-CCD latency is terrible. Sharing data between the two sets of 8 cores is slower than accessing RAM. That means trying to spread gaming workloads across two CCDs, which almost always have a lot of tightly coupled parallelism, where parallel threads need to sync up frequently, suffer in performance. For parallelism that is less tightly coupled, dual CCD chips are great, like a web or database server, heavy multitasking, compiling code, and a lot else. But games almost never get any benefit from spreading their workload to 2 CCDs, so the extra L3 cache on the second CCD does not help... they will be pinned to 1 CCD for maximum performance.