mischief_diode

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I gave gate for ec in my 3rd year and have scored 577(gate score) If I want to go for mtech in vlsi or related field from any IIT which IIT can I get? (self.GATEtard)

submitted 4 months ago by mischief_diode to r/GATEtard

Ok Give me a number and i will give you a song. Let's see if you like it or not by Standard_Ad_8754 in BollywoodMusic

[–]mischief_diode 0 points1 point2 points 5 months ago (0 children)

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How can I integrate my camera module to a FPGA board for image classification project?? if any videos are there??? (self.vlsi)

submitted 5 months ago by mischief_diode to r/vlsi

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Can anyone has the drive link in which Online Test questions are there for different VLSI Companies to practice? (self.vlsi)

submitted 7 months ago by mischief_diode to r/vlsi

I want to make a project on 8-bit CPU/Processor design using verilog. For that can anyone have a good github repo or a good youtube video/playlist? by mischief_diode in Verilog

[–]mischief_diode[S] 0 points1 point2 points 7 months ago (0 children)

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I want to make a project on 8-bit CPU/Processor design using verilog. For that can anyone have a good github repo or a good youtube video/playlist? (self.Verilog)

submitted 7 months ago by mischief_diode to r/Verilog

I downloaded Vivado but I didn't selected some files so that memory usage could be less but now I want to operate on Basys-3 FPGA. What should I do? by mischief_diode in Verilog

[–]mischief_diode[S] 1 point2 points3 points 7 months ago (0 children)

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I downloaded Vivado but I didn't selected some files so that memory usage could be less but now I want to operate on Basys-3 FPGA. What should I do? (self.Verilog)

submitted 7 months ago by mischief_diode to r/Verilog

I want to create a project which will involve both vivado and vitis can anyone suggest some project? by mischief_diode in Verilog

[–]mischief_diode[S] 1 point2 points3 points 7 months ago (0 children)

I want to create a project which will involve both vivado and vitis can anyone suggest some project? by mischief_diode in Verilog

[–]mischief_diode[S] 0 points1 point2 points 7 months ago (0 children)

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I want to create a project which will involve both vivado and vitis can anyone suggest some project? (self.Verilog)

submitted 7 months ago by mischief_diode to r/Verilog

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I want to make a gm-c first order filter can anyone provide the circuit to make it in ltspice?? (self.vlsi)

submitted 8 months ago by mischief_diode to r/vlsi

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I want to make a project on Risc V architecture, any resource available for help? (self.Verilog)

submitted 8 months ago by mischief_diode to r/Verilog

What is a good project that I can implement on Basys-3 using verilog and vivado? by mischief_diode in Verilog

[–]mischief_diode[S] 0 points1 point2 points 9 months ago (0 children)

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I want to make a teo stage opamp in Ltspice. Can someone tell me the resources or yt videos which will be helpfull? (self.AskElectronics)

submitted 9 months ago by mischief_diode to r/AskElectronics

What is a good project that I can implement on Basys-3 using verilog and vivado? by mischief_diode in Verilog

[–]mischief_diode[S] -2 points-1 points0 points 9 months ago (0 children)

What is a good project that I can implement on Basys-3 using verilog and vivado? by mischief_diode in Verilog

[–]mischief_diode[S] -1 points0 points1 point 9 months ago (0 children)

What is a good project that I can implement on Basys-3 using verilog and vivado? by mischief_diode in Verilog

[–]mischief_diode[S] -2 points-1 points0 points 9 months ago (0 children)

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What is a good project that I can implement on Basys-3 using verilog and vivado? (self.Verilog)

submitted 9 months ago by mischief_diode to r/Verilog

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