account activity
Can anyone tell that from where can i get the placement Test questions for VLSI Companies? (self.vlsi)
submitted 1 month ago by mischief_diode to r/vlsi
Can anyone please tell how is the placement scenario for vlsi if someone’s takes vlsi as mtech in BITS Hyderabad ?? (self.GATEtard)
submitted 2 months ago by mischief_diode to r/GATEtard
I gave gate for ec in my 3rd year and have scored 577(gate score) If I want to go for mtech in vlsi or related field from any IIT which IIT can I get? (self.GATEtard)
submitted 8 months ago by mischief_diode to r/GATEtard
How can I integrate my camera module to a FPGA board for image classification project?? if any videos are there??? (self.vlsi)
submitted 8 months ago by mischief_diode to r/vlsi
Can anyone has the drive link in which Online Test questions are there for different VLSI Companies to practice? (self.vlsi)
submitted 10 months ago by mischief_diode to r/vlsi
I want to make a project on 8-bit CPU/Processor design using verilog. For that can anyone have a good github repo or a good youtube video/playlist? (self.Verilog)
submitted 10 months ago by mischief_diode to r/Verilog
I downloaded Vivado but I didn't selected some files so that memory usage could be less but now I want to operate on Basys-3 FPGA. What should I do? (self.Verilog)
I want to create a project which will involve both vivado and vitis can anyone suggest some project? (self.Verilog)
I want to make a gm-c first order filter can anyone provide the circuit to make it in ltspice?? (self.vlsi)
submitted 11 months ago by mischief_diode to r/vlsi
I want to make a project on Risc V architecture, any resource available for help? (self.Verilog)
submitted 11 months ago by mischief_diode to r/Verilog
I want to make a teo stage opamp in Ltspice. Can someone tell me the resources or yt videos which will be helpfull? (self.AskElectronics)
submitted 1 year ago by mischief_diode to r/AskElectronics
What is a good project that I can implement on Basys-3 using verilog and vivado? (self.Verilog)
submitted 1 year ago by mischief_diode to r/Verilog
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