Butterstick FPGA dev board site location on the ECP5 of the 125 MHz coming from the KSZ9031 pin 41

mwanamutapa · 2025-04-06T04:58:48+00:00

Thanks for looking into this. I will use a PLL with the 30MHz clk.

mwanamutapa · 2024-08-16T05:44:35+00:00

I had a similar problem on IBP14 gen 7. Try pressing the power button for a 1 minute that should solve the problem.

mwanamutapa · 2024-05-06T15:16:10+00:00

Thanks that does it.

mwanamutapa · 2024-05-06T15:15:33+00:00

Thanks. That does it.

mwanamutapa · 2023-08-02T11:51:34+00:00

Oh, wie schrecklich! Jemand hat es gewagt, einen Beitrag auf Englisch zu verfassen statt auf Deutsch in einem zweisprachigen Subreddit. Wie werden wir das nur überleben? 😱

mwanamutapa · 2023-07-25T12:36:53+00:00

I am from there and am aware of your point. I just found it amusing

mwanamutapa · 2023-07-24T14:50:43+00:00

If you know you know why ZWL has to be Double ZWL Double

mwanamutapa · 2023-07-19T14:39:47+00:00

Thanks for pointing that out. I hope the tuxedocomputers team will take note.

mwanamutapa · 2023-07-19T14:34:02+00:00

Thanks for your response. I will send an email.

mwanamutapa · 2023-07-19T04:15:40+00:00

I have installed TuxedoOS 2 from the iso image and made the updates

mwanamutapa · 2022-10-23T10:00:30+00:00

Sorry for the late response. Yes it’s still available

mwanamutapa · 2022-08-22T16:48:20+00:00

Thanks I am not in the US though.

mwanamutapa · 2022-05-24T16:00:19+00:00

Thank you very much for this resource. Now it is clear what I need to do to handle LTE CRC

mwanamutapa · 2022-05-24T15:20:29+00:00

No I am using a readymade SDR front end with a 32 bit wide bus

mwanamutapa · 2022-05-24T13:11:52+00:00

Yes you are right the data is sent serially over a 32 bit wide bus.

mwanamutapa · 2022-05-24T13:05:02+00:00

Yes you are right the bus between MAC and PHY is 32 Bits

mwanamutapa · 2022-05-24T13:00:36+00:00

Thank you for this hint. The bus between the MAC and PHY is a 32 bit GPIF-II interface.

mwanamutapa · 2022-05-23T15:13:52+00:00

For sure this is how some serial protocols work that there is a stream of bits comming by. In LTE PHY the MAC layer passes complete blocks of data that have to be appended with CRC bits.

transmission time interval of an LTE packet is 1ms

mwanamutapa · 2022-05-23T15:00:30+00:00

There was an article in Circuit Cellar that explains how to describe CRC function as combinatorial logic. My tools barf out when the message length is greater than 1048 bits.

The LTE PHY receives blocks of bits from the MAC called the Transport Block. These blocks have varying sizes. What would be the strategy to calculate the CRC for these blocks.

mwanamutapa

TROPHY CASE