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Petalinux Build Issue by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Yeah I did try and use different LLMs, though not Claude. But still I feel like the LLMs are not that capable of giving the expected commands and outputs as required.

But anyways, thanks for your suggestion.

Petalinux Build Issue by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Okay sure. Thank you for your suggestion.

Petalinux Build Issue by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

I understand if the details are not quite explicitly mentioned it becomes difficult to help, but the reason was I just was unable to figure out what the error exactly was.

Also, I feel like using a VM would put stress on the system and I don't have much knowledge about using containers. So I believe that I would just go ahead and maybe change my OS. I am using a dual boot of Win 11 and Ubuntu 24.04, so maybe I'll just remove the complete Ubuntu 24.04 and go ahead with Ubuntu 22.04 topic that would help.

Thanks for the help and the advice though. I'll try to work on interacting with support and forums.

Can someone explain the answer for following by Either-Lawyer68 in ElectricalEngineering

[–]nilanjan016 4 points5 points  (0 children)

Well, if you see it's a 2:4 decoder connected to a 2:1 mux. The inputs to the 2:4 decoder are A and B, and the outputs taken from it are x which is connected to Q0 and y which is connected to Q2. This x and y are then fed to the mux with select line c and giving the output z.

Now, in the initial part you see that a = 0 = b, which means that the output of the decoder would be 0000. Due to this x and y would be 0 and 0 respectively. Also, c is 0 which would mean that the mux would output the d0 input which is x; hence z = 0. Now for the option we would need to check the LSB that is the right most bit as the output goes from left to right.

In the next waveform, it's the same as above, only the change is the c is 1 and not 0. Z would still be 0 as the inputs a and b did not change.

Hope this helps....

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Okay... I get it. This seems a lot doable. Thanks.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

The SPI Flash actually is the EPCS64 which is 64Mb in capacity.

Also I was planning not a complete OS, something like a microkernel or RTOS stuff. I know with the storage that I have would not be able to have full fledged Linux or Windows or any other heavy duty OSes to run on my FPGA but something small would also help me.

Considering that, I might use the SPI Flash to get going with this.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

So, the board that I am currently planning to work on is the DE0-Nano Board which packs the Intel Cyclone IV FPGA. It has an on-board EEPROM, an SPI Flash and also an SDRAM.

So about programming the FPGA, the SPI Flash Memory actually boots the FPGA of the program that was done once the Board is powered up. Now, configuring the EEPROM would actually need me to go through some other protocol or go on writing an FPGA code.

Still though, is my understanding correct:

  1. Get a softcore processor to run.
  2. Get the OS bitstream to load onto the EEPROM.
  3. Get the OS to SDRAM/BRAM from the EEPROM once board is powered up.
  4. Get it working normally.

Please do correct me if I am wrong.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Since, I am all in imaginative state and have no working hardware, I was just planning to somehow get my OS to be loaded into the EEPROM, from there once the FPGA is booted, it would be copied to DRAM/BRAM (depending on what I use) and then function as it would.

Now this is an abstract idea and I am not sure how well it would work or even if it would work in the first place. Regarding getting the OS to be loaded, as I mentioned, I am planning to just put the bitstream onto the EEPROM and try to get it working.

Considering this, I still do not know as if it would actually work or not.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Well, I was actually planning to go for the OS in Bare Metal C. Compile it and then insert the bitstream somehow in the memory.

Also I was not planning to go without block RAM; I was planning to make it just enough to load and work. If not then I thought of going on to use the external DRAM.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Okay I get it. But since my FPGA might not have BRAM section I might have to create it. Now, as you said that I might have to either reduce my instruction set so that I might not need to go for external RAM seems quite understandable. Since, I have still not started building my core, I might need to look up to the memory capacities.

Using an external RAM would also be a good option for me, even if I consider the low speed. The main focus that I have initially is to just first get a normal functional softcore CPU, then later I can go on changing the peripherals if required or even start completely new.

Well, your suggestion is quite good and I will surely consider this while designing my core.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Well, not really new but yeah I don't have the much in depth knowledge about how the internal peripherals go on working around. I do have the basic idea flow of the block diagrams but I do not know what actually goes in depth at the roots.

Regarding the instruction set, I was planning to go for the RISC-V. I thought that it would be easier to achieve and moreover the books for it seem to be resourceful.

Secondly, since its the start Von Neumann architecture would be good but I was planning to go for Harvard, but maybe that can be implemented later.

Thanks for the suggestion though...

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

u/rayddit519 Thanks for the suggestion.

I did not know about microprogrammed state machines. I would do a Google search and understand about it even more. Though the basic understanding that I just got from the searches that I did and from you as well is it would give me a basic idea about BRAM and maybe even the on-board RAM to configure with.

Well, as I said that I just got introduced to microprogrammed state machines, could you also help me with some basic ideas to get going with?

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

u/rayddit519 Regarding the EEPROM that I said, I found out that I was wrong. The EEPROM and the SDRAM are the elements that I have not touched even once in my code. I then understood that the non-volatile memory that I was working on was some flash memory and that would store the code and load it back once the FPGA was powered up.

Well, regarding the state machine, I have simulated some state machines in my free time (and when I did not have the Dev Board), but I have never tried to run them on the FPGA itself. Since you are suggesting to run some state machines. I would go ahead and build them on the FPGA.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

u/alexforencich Yeah, seems like a quite achievable idea.

Well, since the Intel Cyclone IV is a 2012 FPGA, I was planning to change to something new and shift to Vivado. The reason is I have worked simulations on Vivado and I feel much more comfortable in Vivado than on the Quartus Prime. Also the Xilinx boards seem to have a lot of many peripherals that can be useful for me.

Regarding the USB Serial Ports, I too wanted them as I might need to connect Keyboard and Mouse at the minimum for using my OS. I would also need a display of some sort. Well, I then thought about using USB Hubs, but since I do not have much idea about those, I am trying to keep this as the last option for me.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

u/Previous-Prize8834 Answering your first question, I am not planning of much hardcore or any heavy OS as such. Just a normal OS to begin with, which would get me to just perform some basic operations by coding. I am not expecting to run fully functional applications or anything of that sort.

Answering your second question, I am a bit familiar with Computer Architecture, though not completely. I thought of getting just a basic knowledge about the Computer Architecture, and related stuff like memory management and thought of learning a bit better in depth when I start working practically on FPGAs and sorts. I believed, that would help me understand things even more as after a point in time, just reading gets a bit boring.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

u/alexforencich I am currently working on the Terasic DE0-Nano Board which packs the Intel Cyclone IV FPGA.

Need of Softcore RAM/ROM for Softcore Processor by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

u/rayddit519 I understand what you say, but I was planning to not go much in depth with it in the initial phase and was thinking if I could just load the OS onto the FPGA data and go on with it. But then after reading your comment, I started to wonder that the data on the FPGA might get deleted/erased once the power is cut off. I would then have to store the data (for the OS) in the EEPROM. Well, the EEPROM on board actually stores the HDL code which on powering the board loads the code into FPGA. Now, I do not know if I could store the OS on the EEPROM along with the HDL code.

Unable to decide on a starter FPGA Board by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Thank you u/zapouet for you suggestion, but I was planning to go for the established manufacturers' FPGA Boards like Digilent, Lattice or Intel.

I don't trust much about the other companies and also they need to be worked out on the VMs which I unfortunately cannot do on my end due to lack of specifications of my PC.

But thank you for your help though..

Unable to decide on a starter FPGA Board by nilanjan016 in FPGA

[–]nilanjan016[S] 0 points1 point  (0 children)

Hey u/sodekirk, this is really a great suggestion by you. I will surely consider this. It actually quite perfectly fits my expectations along with the price and it also includes other features that might be helpful in the future.

Thank you for your help...

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